Source: Samsung Electronics

Kye Hyun Kyung, head of Samsung’s semiconductor and device solutions (DS) division, has previously publicly stated that he will surpass TSMC and other industry giants in the next five years.

According to internal sources cited by Korean news media Money Today, Samsung’s semiconductor foundry unit is rapidly advancing its 2nm production plan. Samsung is integrating superior resources to accelerate the research and development of 2nm technology. Some industry insiders are even speculating that Samsung may skip 3nm production and jump directly to the 2nm manufacturing process.

It was reported in June this year that Samsung officially announced the latest process technology roadmap. The company plans to launch the 2-nanometer SF2 process in 2025 and the 1.4-nanometer SF1.4 process in 2027. At the same time, the company also unveiled some features of its SF2 process.

Samsung’s SF2 process is further optimized based on the third-generation 3-nanometer (SF3) process launched earlier this year. Compared with SF3, the SF2 process can improve power consumption efficiency by 25% at the same frequency and complexity, improve performance by 12% at the same power consumption and complexity, and reduce power consumption by 5% at the same performance and complexity. area.

To make the SF2 process more competitive, Samsung will also provide a series of advanced IP portfolio for the process, including LPDDR5x, HBM3P, PCIe Gen6 and 112G SerDes.

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Samsung’s SF2 process is further optimized on the basis of the third-generation 3nm-scale (SF3) process introduced earlier this year. Compared with SF3, the SF2 process can improve power efficiency by 25% at the same frequency and complexity, improve performance by 12% at the same power consumption and complexity, and reduce 5% at the same performance and complexity area. In order to make the SF2 process more competitive, Samsung will also provide a series of advanced IP combinations for the process, including LPDDR5x, HBM3P, PCIe Gen6 and 112G SerDes, etc.

Following SF2, Samsung will launch SF2P optimized for high-performance computing (HPC) in 2026, and SF2A optimized for automotive applications in 2027. Also in 2027, the company plans to start mass production using the SF1.4 (1.4 nanometer scale) manufacturing process. Samsung’s 2nm process will be roughly in sync with TSMC’s N2 (2nm) process, and about a year behind Intel’s 20A process.

It is noticed that in addition to continuously improving its own process technology, Samsung OEM also plans to continue to develop its radio frequency technology. The company expects its 5nm RF process technology to be ready in the first half of 2025. Compared with the old 14nm RF process, Samsung’s 5nm RF process is expected to improve power consumption efficiency by 40% and increase transistor density by about 50%. In addition, Samsung will start producing gallium nitride (GaN) power semiconductors in 2025 for various applications including consumer goods, data centers and automotive fields.

In terms of expanding technology supply, Samsung Foundry remains committed to expanding its manufacturing capabilities in Pyeongtaek, South Korea, and Tyler, Texas, USA. Samsung plans to start mass-producing chips at its Pyeongtaek 3 production line (P3) in the second half of 2023. The new Taylor City facility is expected to be completed by the end of this year and begin operations in the second half of 2024. Samsung’s current plan is to increase its cleanroom capacity by 7.3 times by 2027 compared to 2021.

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In a nutshell, this approach gives an alternative to process indentation and 3D packaging: developing the backside of the wafer.

In the foundry market, technology is evolving from high-k metal gate planar FETs to FinFETs to MBCFETs and now BSPDNs, Park said.

The FinFET (called 3D transistor in the past) mainly used at this stage is the key chip design technology in the development of the 10nm process. Reduce leakage (electron leakage), but the development of 5nm or even 3nm process means that FinFET will be outdated, so the industry has developed a four-sided all-gate or GAA technology.

The factory then added what it calls nanosheets instead of nanowires to this, and dubbed the technology MBCFETs. But BSPDN here is different and can be understood as an evolution of the chiplet design used by Samsung, Intel and TSMC.

With the chiplet technology solution, we can apply the same process on a single chip, or connect various chips manufactured by different processes from different foundries. This is also the technical solution adopted by Intel’s 14th-generation Core and AMD Ryzen. It is also called For 3D-SoC, logic circuits and memory modules can be combined together at the same time.

According to reports, BSPDN is different from the front-end power supply network, which mainly uses the back-end; the front will have logic functions, while the back will be used for power supply or signal routing.

The concept of BSPDN was first proposed at IMEC in 2019, when a 2nm paper citing the technology was also published at IEDM in 2021.

In this Korean paper titled “SRAM Macro and Logic Design and Optimization Using 2nm Process Back-End Interconnection”, the author proposes to move functions such as the power supply network to the back of the chip to solve the problem of wiring congestion caused by using only the front side. Compared to FSPDN, BSPDN is said to provide 44% better performance while 30% more power efficient.

Eric Beyne, Senior Fellow, Vice President of R&D and Program Director of 3D Systems Integration at Imec, said: “A chiplet involves a chiplet that is individually designed and processed. A well-known example is high-bandwidth memory (HBM) – also known as dynamic random access. A stack of memory (DRAM) chips. This memory stack is connected to the processor chip through an interface bus, which limits their use to latency-tolerant applications. As a result, the chiplet concept will never allow the fast access to and from mid-level cache memory.”

With 3D-SOC integration, we can implement logical partitioning of memory using direct and shorter interconnects, resulting in significantly improved performance. In the paper, the authors show an optimized implementation of a 3D-SOC design with the memory macros at the top of the die and the rest of the logic at the bottom of the die—a full 40% increase in operating frequency compared to the 2D design.

One possible partition of a high-performance 3D-SOC system involves placing some or all of the memory macros at the top of the die and logic at the bottom of the die.

On the technical side, this can be achieved by bonding the active front side of the “logic wafer” to the active front side of the “memory wafer” using low temperature wafer-to-wafer bonding. In this configuration, the original backsides of both wafers are now outside the 3D-SOC system.

Eric Beyne said: “We can now consider utilizing the ‘free’ backside of these chips for signal routing or directly powering transistors in the ‘logic wafer’. Traditionally, signal routing and power delivery have occurred on the front side of the wafer, where they are Competing for space in complex back-end interconnect schemes. In these designs, the backside of the silicon is used only as a carrier. In 2019, Arm’s simulations showed for the first time the beneficial effects of using BSPDN in a CPU) design implemented by imec Developed 3nm process. In this design, the interconnect metal on the backside of the wafer thinning is connected to the 3nm transistors on the front side of the silicon wafer using through-silicon vias (TSVs) on buried power rails.

Therefore, additional performance gains can be expected when BSPDN is implemented to provide power-hungry core logic circuitry at the bottom of a “logic memory” 3D-SOC. Alternative 3D-SOC partitions can also be considered, where some memory blocks, such as L1-level cache static random access memory (SRAM), are also in the bottom die, also powered from the backside.

In addition to expanding the possibilities of 3D-SOC designs, BSPDN has also been proposed for monolithic single-chip logic and SRAM system-on-chip (SOC), which can aid further device and IC expansion.

Geert Van der Plas, project manager at imec, said: “Moving the power supply network to the backside of the silicon has proven to be an interesting approach to solve the back-of-the-line (BEOL) routing congestion challenges and reduce IR drop. This is similar to the 3D-SOC approach. The main difference is that the dummy wafer is now bonded to the target wafer for backside wafer thinning and metallization.” One of imec’s partners announced at the time that it would be implemented in one of its future node chips Such a BSPDN concept.

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The world’s second-largest foundry behind TSMC aims to mass produce advanced 2nm technology chips by 2025 and 1.4nm chips by 2027, which will be used for applications such as high-performance computing and artificial intelligence.

“Some progress has been made this year (in raising prices) and costs are being reflected …… ” said Moonsoo Kang, executive vice president of Samsung Electronics’ foundry business, “New orders won so far will be made in 2-3 years, so the immediate impact of the current environment will be minimal.”

Samsung began mass production of chips using 3nm technology in June this year. Samsung said the company is in talks with potential 3nm partners, including Qualcomm, Tesla and AMD, among others.

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On the last day of June, Samsung announced the official mass production of the 3nm process, this time Samsung was finally ahead of TSMC to take the lead in mass production of a new generation of process and is bending the curve, the latter’s 3nm will only be mass-produced in the second half of this year.

According to Samsung’s official introduction, on the 3nm chip, it abandoned the previous FinFET architecture and adopted the new GAA transistor architecture, which significantly improved the chip’s power performance.

Compared to 5nm, the newly developed 3nm GAE process is able to reduce power consumption by 45%, reduce area by 16%, and improve performance by 23% at the same time.

The second-generation 3nm GAP process can reduce power consumption by 50%, improve performance by 30%, and reduce area by 35% at the same time for better results.

What about further down the line? Samsung also has a plan, after the 3nm GAP process will usher in the 2nm GAP process, also based on nanosheet technology GAA transistors, but the structure is further optimized, from 3 nanosheets to 4, which can improve the drive current, while also optimizing the stacking structure to improve performance and reduce power consumption.

2nm GAP process mass production time is also set, is expected to mass production in 2025, the timing and TSMC power production 2nm process is about the same, and is likely to be technically ahead of the latter, because TSMC’s 2nm process in the transistor density squeeze toothpaste, improve only 10%.

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