Both companies are described as key members of RISC-V International and the RISC-V Software Ecosystem (RISE) program, and both are strong advocates of open architectures.

Ventana Micro Systems was founded in 2018, and its first product is the Veyron V1, which launches at the RISC-V Summit in December 2022; Ventana will be launching the Veyron V2 next week, and this co-innovation outcome is expected to be centered around that goal as well.

The main change in V2 over V1 is said to be that the RISC-V ISA will have most of the necessary features to compete with x86 / Arm, such as standard vector extensions and the IOMMU specification. It will include:

• Hypervisor extension
• Type 1 and Type 2 hypervisors; nested virtualization
• Advanced Interrupt Architecture (AIA)
• Includes native MSI processing and interrupt virtualization
• External and self-hosted debugging; memory tracing
• Rich set of performance events and performance counters

A query revealed that the RVA23 feature set includes UCIe chip interfaces, 40% performance improvement, 512b Vector Units + AI Matrix Extension, server-grade IOMMU and RISE software compatibility platforms, and Domain Specific Acceleration (DSA).

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▲ Picture source Google Blog

It is learned after inquiries that at the RISC-V Summit held at the end of last year, Google announced plans to make RISC-V a T1-level support architecture for Android, raising the status of the RISC-V architecture to the same level as ARM processors.

The Android Open Source Project (AOSP) has begun accepting RISC-V patches since September last year, and has now entered the mature support stage. Google claims that developers can now build and test on their own machines. and Android running RISC-V.

▲ Picture source Google Blog

Google also said that later this year, developers can more easily debug riscv64 Android applications, and by next year, Google plans to publicly provide a RISC-V version of the Android emulator.

▲ Picture source Google Blog

However, AOSP’s support for RISC-V is still relatively primitive at this stage, and the fully optimized backend of Android Runtime (ART) is still under development.

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VisionFive 2 is the world’s first high performance mass production RISC-V single board computer (SBC) with integrated 3D GPU, and it is actively adapted by RISC-V software developers, including openEuler, openKylin, Ubuntu, etc.

▲ VisionFive 2, image source Saifang Technology

▲ VisionFive 2 hardware parameters

The new version of deepin’s VisionFive 2 development board for RISC-V architecture has been released.

The test image is based on the released deepin V23 Beta version, using the vendor’s open source firmware and kernel branch, integrating deepin related system components. After RISC-V SIG adaptation and testing, the basic system, wired network, USB interface and other basic modules can be used normally, and can support HDMI output and graphical interface display, DDE desktop environment is running normally.

▲ Picture source deepin operating system official account

▲ Picture source deepin operating system official account

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The company’s first product, Milk-V Duo, is a miniature single-board computer with a 1GHz dual-core chip, priced from $9 (currently about RMB 64). An unnamed quad-core system with a StarFive JH7110 processor and a Raspberry Pi-like design will be available soon. Now, the more powerful Milk-V Pioneer platform packs 64 RISC-V cores into a miniature ATX motherboard.

MILK-V Pioneer is powered by the compute SG2042 processor with 64 Genesis C920 64-bit core CPUs running at 2GHz; the motherboard supports up to 128GB of 4-channel DDR4-3200 memory thanks to 4 DIMM slots and features 5 SATA connectors, two PCIe 3.0 x4 M.2 slots and A microSD slot for storage.

Additional ports and connectors include:

• 1 M.2 E-Key for wireless NIC
• 2 x 2.5 GbE Ethernet ports
• 8 USB 3.2 Type-A ports (10 Gbps)
• 24-pin ATX power connector
• 1 PCIe x16 graphics card slot

The board measures 244 mm x 244 mm (9.6″ x 9.6″) and is suitable for most cases designed for micro ATX motherboards.

MILK-V also plans to offer a “Pioneer Box” with 64GB of RAM, 1TB of storage, Intel X520-T2 NIC with two 10 GbE RJ45 ports, AMD R5 230 graphics with HDMI, VGA and DVI ports, 350W MSI A350 power supply, and chassis and cooling fans.

According to Milk-V, the development board is available for Fedora, Debian, Ubuntu, Arch, and Deepin operating systems.

The Milk-V Pioneer motherboard is priced at RMB 6,999 in China and the Milk-V Pioneer mainframe is priced at RMB 9,999 in China.

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QEMU (Quick Emulator) is one of the mainstream equipment emulation software in the industry. It can run operating systems and programs that support other architectures on a physical machine of one architecture (such as X86 PC), so that the software can run on different hardware architectures without awareness. For software developers, QEMU can provide a platform for system execution under different hardware architectures, as well as a software cross-architecture integrated testing environment to improve software development efficiency and maturity.

A year after the release of QEMU 7.0, the QEMU 8.0 release brings improved support for ARM and RISC-V architectures. For ARM, added emulation support for FEAT_EVT, FEAT_FGT, and AArch32 ARMv8-R; CPU emulation support for Cortex-A55 and Cortex-R52, support for the new Olimex STM32 H405 device type, gdbstub support for M-profile system registers, and more.

For RISC-V architectures, QEMU 8.0 brings updated device support for OpenTitan, PolarFire and OpenSBI, additional ISA and extensions to support smstateen, support for native debug icount triggers, cache-related PMU events in virtual mode, Zawrs / Svadu / T-Head / Zicond extensions and ACPI etc.

Additionally, RISC-V received several fixes covering PMP propagation for the TLB, mret exceptions, uncompressed instructions, and other emulation/virtualization improvements.

For HP Precision Architecture (HPPA) platforms, QEMU version 8.0 improves fid (floating point awareness) instruction support and 32-bit emulation.

On the other hand, the s390x (IBM Z) platform supports asynchronous teardown of secure KVM guest memory during reboot and improved handling of zPCI passthrough devices.

For x86, the latest QEMU 8.0 release introduces new Intel SapphireRapids CPU support, support for Xen guests under KVM with Linux kernel 5.12 and higher, and TCG support for FSRM, FZRM, FSRS, and FSRC CPUID flags.

Among other notable changes, QEMU 8.0 improves virtio-mem, supports using preallocation with live migration, updates experimental migration support for VFIO migration protocol v2, and improves TCP efficiency and use of qemu-nbd Efficiency over TLS.

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At the meeting, the two parties discussed in-depth cooperation based on openKylin and Saifang 7110 and next-generation chips and reached a cooperation intention to continue to promote the ecological development of RISC-V software and hardware.

The openKylin community said that in the future, the two parties will continue to deepen cooperation, promote the compatibility and adaptation of RISC-V architecture chips and openKylin operating systems, and work together to develop and explore the RISC-V ecosystem.

Saifang 7110 is the Fang·Jinghong 7110 SoC (JH7110 for short) released by Saifang Technology in August 2022. It adopts TSMC’s 28nm process and is equipped with a 64-bit quad-core RISC-V CPU with a working frequency of 1.5GHz. 2MB of L2 cache. JH7110 is a multimedia processor integrating 3DGPU, H.264 / H.265 video codec IP and ISP IP.
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Due to the slowdown of IoT infrastructure, coupled with the long life cycle of IoT devices and fragmented applications, unless there are new specifications or emerging applications, it will prompt chip vendors to develop new chips. In addition to the mature NB-IoT and LTE-M chip markets, the prospect of LTE Cat.1bis technology development is attracting attention from chip makers, prompting Qualcomm and many others to launch new chips supporting LTE Cat.1bis. In addition, 5G NR-Light (also known as RedCap) technology is the focus of future cellular IoT development, Qualcomm has taken the lead in the industry to publish related chips and forecasts that IoT devices equipped with related chips will be available in the first half of 2024.

The report points out that cellular IoT chip makers such as CoreTech and Corewing Information have launched IoT chips with RISC-V architecture, which is an option to jump out of the Arm architecture ecosystem and strengthen chip autonomy.

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Hardware Support

In terms of hardware, openEuler RISC-V 23.03 has inherited and updated Quanzhi Nezha D1, Sisu Lichee RV, SiFive Unmatched, Saifang VisionFive 1 and other development boards, and also updated and supported Saifang VisionFive 2 and computing power SG2042 Two devices.

Support SG2042

The innovative version of openEuler RISC-V 23.03 is successfully connected to the RISC-V 64 cores high-performance processor SG2042 (EVB) server board, which is an important step in the ecological development of the RISC-V server field. After testing, the basic system, wired network, USB interface and other components can be used smoothly. Compared with the qemu user mode, the local construction method of SG2042 has a significant speed advantage, which greatly shortens the construction time for this release of openEuler RISC-V 23.03. The RISC-V SIG plans to combine SG2042 with the OBS build system to improve the efficiency of building openEuler RISC-V software packages.

Update VisionFive 2

openEuler RISC-V 23.03 has made major repairs to the VisionFive 2 development board. On the basis of the previous test image, the graphical interface, HDMI output and other parts have been repaired. The available functions have been matched with other development boards, and the overall operation is relatively smooth.

Software Support

Kernel Upgrade

openEuler 23.03 uses the Linux Kernel 6.1 kernel, and uses the 6.x kernel for the future openEuler long-life cycle version to conduct technical exploration in advance. RISC-V SIG followed up this important update and provided the 6.1 kernel adaptation for the openEuler RISC-V environment. It is convenient for RISC-V developers to use the latest kernel development.

Support for multiple desktop environments

In terms of desktops, the innovative version of openEuler RISC-V 23.03 supports XFCE, UKUI, DDE, Kiran, GNOME, and Cinnamon desktop environments, providing users with an excellent desktop user experience. RISC-V SIG has also optimized some desktop components such as GNOME’s gjs.

Adapt to iSulad container

The RISC-V SIG has added RISC-V support to iSulad and successfully tested the availability of the iSulad container engine in the openEuler RISC-V 23.03 innovation release. iSulad is a container engine project under the Open Atom Open Source Foundation, initiated by Huawei Poincaré Laboratory, and open sourced in the openEuler community in 2019.

Compared with Docker, iSulad Universal Container Engine is a new container solution that provides a unified architecture design to meet the different needs of CT and IT fields. It is implemented in C/C++ and is characterized by lightness, flexibility, ingenuity, and speed. It is not limited by hardware specifications and architecture and has a lower noise floor overhead and a wider range of applications.

Experimental JIT support

In the innovative version of openEuler RISC-V 23.03, RISC-V SIG added targeted JIT optimization and testing, related work involved Mesa, GNOME desktop optimization and LuaJIT related software.

Currently, the RISCV SIG has upgraded Mesa to version 23.0.0, and introduced a new JIT engine based on LLVMpipe that supports RISC-V optimization. At the same time, the glxgears test was run in the RISC-V environment, confirming that the performance has been significantly improved. The developers are adding Cache optimization based on the patch, and we will continue to follow up on the follow-up progress.

On the desktop side, the RISC-V SIG has backported the SpiderMonkey RISC-V JIT patch on mozjs102, which significantly improves the performance of gjs and further optimizes the GNOME desktop experience.

Based on the experimental addition of LuaJIT support, the RISC-V SIG has successfully built a series of LuaJIT-dependent packages for the RISC-V architecture, including openResty and Minetest, and related support is still under development.

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▲ Source SiFive official website

The development board, which will be available in summer 2023, is powered by the Intel Horse Creek SoC, which is based on the Intel 4 process and includes a SiFive Performance P550 Core Complex quad-core application processor. The processor supports chaotic pipeline, RISC-V RV64GBC ISA, on-board DDR5-5600 and PCIe Gen5.

With 2x PCIe expansion slots, 1/10 GbE networking, USB 3, on-board graphics and remote management-ready interface (OCP DC-SCM), it is claimed to be suitable for developing desktop and rack-based build/test/deployment servers for RISC-V software development.

▲ Picture source Intel official community

The foreign media WikiChip Fuse captured the physical picture of the HiFive Pro P550. The size of the Horse Creek SoC is only 4 mm x 4 mm, and it is packaged in a 19 mm x 19 mm BGA package. The price information of the product is not yet clear. We can look forward to it.

▲ Image Source WikiChip Fuse

▲ WikiChip Fuse

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First of all, let’s talk about the Baikal-S (Baikal) processor, which was developed in Russia. This processor from the Russian company Baikal Electronics has 48 cores based on the Arm instruction set architecture (ISA).

Its 48 cores have a baseline frequency of 2.0 GHz, a maximum acceleration of 2.5 GHz, a thermal design power consumption of 120 W, support for quad parallelism, and the integration of a RISC-V architecture co-processor, also developed in-house, for secure boot and management, with performance roughly comparable to Intel Xeon Gold 6148 (20 cores @2.4 GHz) or AMD Skyline 7351 (16 cores @2.9 GHz).

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Russian company Eliptech now offers a companion server motherboard, the ET113-MB, which provides six 72-bit storage interfaces, supports up to 768GB of DDR4-3200 ECC memory (128GB in a single channel), five PCIe 4.0 x16 slots, and offers a USB 2.0 controller, two Gigabit LAN ports, and three SATA and four U.2 and various other general purpose I/O ports.

While this product looks good on paper, it’s pretty much just symbolic. Because the Baikal-S1000 processor (manufactured using TSMC’s 16nm process) is no longer available in mass production due to geopolitical conflicts, the CPU used on this motherboard is still a non-mass production version.

Considering the extraordinary I/O capabilities of the Baikal BE-S1000 processor, it can support a considerable number of storage devices. However, the Eliptech ET113-MB motherboard has four U.2 ports, and they are all located on the outside, so the usefulness is somewhat limited.

At the same time, there are multiple slots for external boards on this motherboard, but they are a bit awkwardly positioned, so you won’t be able to install external card products unless you remove the bracket. The motherboard also has an audio connector, which means it can be used to create a desktop workstation, although it’s unclear how to use a desktop workstation without a graphics card.

From the looks of it, this motherboard uses the SSI MEB specification, which means it could theoretically be used for server/storage systems, but that’s debatable given the number of 3.5-inch or 2.5-inch drives.

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