High-performance RISC-V CPU design company Ventana joint Imagination co-development of heterogeneous CPU-GPU SoC, the two companies will be at next week’s RISC-V Summit to show its simulation model.
Both companies are described as key members of RISC-V International and the RISC-V Software Ecosystem (RISE) program, and both are strong advocates of open architectures.
Ventana Micro Systems was founded in 2018, and its first product is the Veyron V1, which launches at the RISC-V Summit in December 2022; Ventana will be launching the Veyron V2 next week, and this co-innovation outcome is expected to be centered around that goal as well.
The main change in V2 over V1 is said to be that the RISC-V ISA will have most of the necessary features to compete with x86 / Arm, such as standard vector extensions and the IOMMU specification. It will include:
- Hypervisor extension
- Type 1 and Type 2 hypervisors; nested virtualization
- Advanced Interrupt Architecture (AIA)
- Includes native MSI processing and interrupt virtualization
- External and self-hosted debugging; memory tracing
- Rich set of performance events and performance counters
A query revealed that the RVA23 feature set includes UCIe chip interfaces, 40% performance improvement, 512b Vector Units + AI Matrix Extension, server-grade IOMMU and RISE software compatibility platforms, and Domain Specific Acceleration (DSA).
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