One of the first 2nm data center CPUs, Monaka will use about 150 enhanced Armv9 cores and support accelerators, have the SVE2 instruction set, the vector length can vary from 128bit to 2048bit, and be equipped with SRAM chips and I/O chips. It will support DDR5 memory, PCIe 6.0 connectivity, and CXL 3.0 interconnect.

It is worth mentioning that the successor to Riken’s supercomputer “Fugaku” is planned to be launched around 2030. As such, Monaka is primarily competing for the emerging data center market rather than solving supercomputer performance problems.

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Fujitsu introduced its next-generation data center processor, MONAKA, to media and analysts at a research strategy briefing at its Kawasaki plant on Wednesday.

The company plans to launch the processor in fiscal 2027, which will use Arm architecture and TSMC’s 2nm process and will achieve twice the energy efficiency of competitors.

Naoki Shinjo, general manager of Fujitsu’s advanced technology development department, said: “The amount of data processed globally in 2030 is expected to reach 10 times that of 2020, and is expected to continue to grow explosively thereafter.” He believes that data will “increase as the amount of data increases. , the demand for large data centers will also increase, but unless we reduce energy consumption, it will be difficult to achieve carbon neutrality.”

FUJITSU-MONAKA aims to significantly improve the energy efficiency of data centers and pursue high-speed data processing required for AI and DX.

According to reports, the processor is based on Fujitsu’s unique technologies, such as the micro-architecture and low-voltage technology cultivated by supercomputers K and Fugaku. It also uses Arm’s latest architecture “Armv9-A” and TSMC’s 2nm process, and will also use 3D Chiplet packaging technology. wait.

Fujitsu said that the number of processor cores they are currently developing is about 150, supports SVE2 SIMD, supports DDR5 memory, the external interface supports PCI Express 6.0 (CXL 3.0), and the cooling system supports air cooling.

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TSMC’s Kaohsiung factory is also currently actively “preparing for war” and is expected to use backside power supply technology to mass-produce the N2P (2nm enhanced version) process one year after the launch of the N2 process.

It was previously reported that TSMC had previously revealed information that by expanding the backside power rail solution on the N2 process to reduce infrared attenuation and improve signals, performance can be improved by 10% to 12% and the logic area can be reduced by 10%. to 15%.

TSMC plans to deliver backside power rail samples to customers in the second half of 2025 and mass production in 2026.

Samsung’s previously announced semiconductor plan calls for mass production of 2nm in 2025 and 1.4nm in 2027; while Intel is expected to mass produce 20A using Gate All Around (GAA) technology RibbonFET transistor architecture in the first half of 2024. 18A will be mass-produced in 2025.

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In this regard, TSMC responded this evening that it has a professional team responsible for 2nm R&D operations, but did not disclose the details of the staffing.

On August 15, TSMC’s Zhongke 2nm plant confirmed that it will delay the construction of the plant until next year, so TSMC decided to directly cut the Kaohsiung plant into the 2nm project.

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TSMC’s main 2nm production plan will first be placed in Baoshan, Hsinchu. TSMC is internally designated as Fab 20, and plans to build four plants from P1 to P4. P1 is currently in full swing and is expected to be realized next year. Trial production, mass production in the second half of 2025.

According to TSMC supply chain sources, TSMC has notified equipment manufacturers to start delivering 2nm-related machines in the third quarter of next year, and the Kaohsiung plant’s 2nm installation is estimated to be only one month later than the Hsinchu Baoshan plant.

According to the currently known information, TSMC plans to build two 12-inch wafer fabs at the former site of CNPC’s Kaohsiung refinery, including the first phase of 7nm and 6nm fabs with a monthly production capacity of 40,000 wafers, and the second phase of a monthly production capacity of 20,000 wafers. 28nm and 22nm fabs. If the investment plan is confirmed, the first phase of the fab will be completed in 2024 and will enter mass production in 2025, but now it seems that it has chosen to cut into the 2nm project for various reasons, and the specific plan is still uncertain.

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Rapidus CEO Junyoshi Koike said in an interview with Nikkei and Tokyo Economic News that Rapidus’ 2nm chips are crucial for Japan, as some will be used in high-performance computing applications that are critical to national security, while others will be used in innovative civilian applications such as self-driving cars and robots.

According to official plans, Rapidus’ factory in Wakkanai (Chitose), Hokkaido is scheduled to start trial production of 2nm chips in April 2025.

The factory is expected to start trial operation of water, electricity, gas and ventilation systems in September 2024 in preparation for the installation of production tools in December of the same year, and the large-scale production line is expected to be put into operation in early 2027.

Koike said Rapidus has recruited 100 semiconductor engineers by April 2023 and plans to double that number by the end of the year. The first engineers are currently being trained at IBM’s Albany NanoTech Complex. The company believes it will need 300 to 500 engineers to enter trial production in 2025.

The 2nm plant in Wakkanai is said to be divided into three or four phases, which the company calls an “Innovative Integrated Manufacturing” (IIM) unit. The IIM-1 unit will manufacture 2nm chips, while the IIM-2 will handle more advanced chip processes than 2nm.

Rapidus was established in August 2022 and was jointly funded by 8 Japanese companies including Toyota, Sony, NTT, NEC, Softbank, Denso Denso, Kioxia, and Mitsubishi UFJ Bank. It is estimated that Rapidus needs a budget of 5 trillion yen from R&D to mass production.

The Japanese government has agreed to subsidize the company for two years totaling $2 billion. However, other Japanese companies seem reluctant to invest in Rapidus. But because the company needs a lot of money, its CEO is considering raising more money through an initial public offering (IPO), but nothing has been announced yet.

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Rapidus CEO Junyoshi Koike told Nikkei in an interview that he is in talks to supply semiconductors to some of the largest U.S. technology companies. “We are looking for an American partner and we have started talking to some GAFAM companies. Specifically, there is demand from data centers,” he said.

Rapidus was established in August 2022. It was jointly funded by eight Japanese companies including Toyota, Sony, NTT, NEC, Softbank, Denso, Kioxia, and Mitsubishi UFJ Bank.

Koike Junyi, president of Japanese semiconductor company Rapidus, previously said: It is planned to build a 2nm prototype line by the first half of 2025 at the earliest. It will take 2 trillion yen to establish the technology, and 3 trillion yen will be needed to prepare for the mass production line.

The first prototype of this 2nm semiconductor trial production line will be completed in 2025, and then mass production will begin in 2027, in order to catch up with world-class semiconductor manufacturers such as TSMC as soon as possible, and the latter plans to mass produce 2nm process technology in 2025.

It is worth mentioning that the technical difficulty required for 2nm mass production is greatly improved compared with existing technologies. Although TSMC has a factory in Kumamoto Prefecture, Japan, this semiconductor factory, which is scheduled to start mass production in 2024, can only produce 12-28 nanometer products.

In addition, Rapidus signed a technology licensing agreement with IBM in the United States at the end of 2022, and IBM has successfully trial-produced 2nm products in 2021. Rapidus will send employees to the United States in the near future to master the required basic technologies.

Koike Junyi previously stated that the Rapidus expert team now has about 100 people, and the first batch has completed relevant training in IBM in New York State. IBM, a major technology contributor to Rapidus, demonstrated a storage prototype made with 2nm technology in 2021.

Rapidus plans to develop a “Rapidus Edition” manufacturing technology based on IBM’s 2nm process technology, start trial production of logic semiconductors in 2025, and mass-produce in 2027. Production technologies for Rapidus releases are focused on two main areas:

 "High-Performance Computing (HPC)" Chips Expected to Grow in Demand

 "Ultra Low Power" chips predicting the future of smartphones

Koike Junyi said in the interview that Rapidus will independently test and package the semiconductor components it manufactures, which will not only shorten the length of the production cycle, but also increase profits.

Rapidus hopes to implement rapid feedback on the processing of each silicon wafer, which will greatly speed up the process of identifying defects and problems, and ultimately speed up the time-to-market of finished products.

It is said that Rapidus will not compete with TSMC, but prefers to continue to be a niche manufacturer focusing on the server field, the automotive industry, communication networks, quantum computing and smart cities.

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AMD has never mentioned Zen 6 in official promotional materials. The latest roadmap was released in June 2022, saying that Zen 5 will be launched in 2024. So we have a long wait to see Zen 6.

According to Zaheer’s dynamic content, the internal codename of the Zen 6 core is Morpheus but did not share the codename information of CCD (Core Complex Die).

According to reports, the Zen 6 chip uses a 2nm manufacturing process. Since the release is still far away, it is currently impossible to confirm whether TSMC or Samsung will be used for mass production of CCD.

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ASML announced last year that it would expand its investment in Taiwan and plan to build a factory in Linkou, with the first investment phase amounting to NT$30 billion and about 2,000 employees moving in. In addition, ASML also submitted an application to the Ministry of Economic Affairs (MOEA) last year, proposing an R&D subsidy program for 2nm wafer optical measurement equipment, which has been accepted by the MOEA for review.

The Ministry of Economic Affairs’ “A+ Enterprise Innovation R&D Cultivation Program” aims to subsidize enterprises to carry out innovative R&D and forward-looking industrial technology development, with an annual budget of about NT$2 billion (currently about RMB 450 million). The program attracts major international manufacturers to Taiwan for R&D and production and helps companies in the region to enter the supply chain of front-end devices.

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The first prototype of this 2nm semiconductor pilot line will be built in 2025, and then mass production will begin in the “late 20s” to catch up with world-class semiconductor manufacturers such as TSMC, which plans to mass produce the 2nm process in 2025.

Rapidus was established in August 2022, by Toyota, Sony, NTT, NEC, Softbank, Denso Denso, Armor Man, Mitsubishi UFJ Bank and other eight Japanese companies jointly funded the establishment of the amount of 7.3 billion yen, in addition to the Japanese government also provided a 70 billion yen grant as a research and development budget.

According to the report, Rapidus plans to formally decide on the site of the prototype 2nm production line facility by March, which is also expected to handle the subsequent mass production work. Junji Koike said the site will require a stable utility infrastructure and the ability to “easily attract domestic and foreign talent.

The more delicate and complex the circuitry of a cutting-edge semiconductor, the longer it takes from design to mass production. President Koike said that the system for providing design support to user companies and the mass production process will be adjusted to shorten the time required for mass production. The goal is to differentiate ourselves from TSMC and Samsung in Korea, which are far ahead in terms of volume, by offering cutting-edge products in a short period of time. President Koike said that in the future, “we will aim to establish a high-yield business model with a system that only mass-produces cutting-edge products.

It is worth mentioning that the technical difficulty required for 2nm mass production is much higher than the existing technology. Although TSMC has a factory in Kumamoto Prefecture, Japan, the semiconductor factory scheduled to start mass production in 2024 can only produce 12 to 28 nm products.

In addition, Rapidus signed a technology licensing agreement with IBM in late 2022, and IBM has successfully piloted 2nm products in 2021. Rapidus will be sending employees to the U.S. in the near future to become proficient in the underlying technology required.

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It is reported that Rapidus is a high-end chip company jointly invested by eight Japanese giants, including Toyota, Sony, Kaixia, NTT, Denso, NFC, Mitsubishi and Softbank. RMB) subsidy.

Rapidus comes from Latin, which means “fast”. Rapidus mainly aims to mass-produce advanced semiconductors below 2nm that have not yet been practically used in the world.

The memorandum was signed by Yasutoshi Nishimura, Minister of Economy, Trade and Industry of Japan, Jan Youngbon, Minister of Foreign Policy, Culture, Digitalization and Facilities of Flanders, Belgium, Atsuyoshi Koike, President and CEO of Rapidus, and Luc Van, President and CEO of IMEC. den hove sign.

Rapidus plans to mass-produce 2nm chips in Japan in the second half of the 2020s, which will be used in 5G communications, quantum computing, data centers, self-driving cars and digital smart cities, among other fields. IMEC intends to support Rapidus in research and development of cutting-edge technologies.

To this end, the two parties expressed their intention to establish a strategic partnership, Rapidus will become a core partner of IMEC’s advanced nanoelectronics project, and the memorandum also mentions cooperation with the upcoming Frontier Semiconductor Technology Center (LSTC), which will serve as R&D center for post-2nm technology in Japan.

According to Nikkei, Rapidus President Atsuyoshi Koike admitted that Japan is 10-20 years behind in cutting-edge technology nodes, and it will not be easy to turn around.

Japan’s Ministry of Economy, Trade and Industry (METI) said Imec and Rapidus intend to conduct bilateral projects on key technologies such as EUV lithography, and Rapidus may send engineers to Imec for training. In turn, Imec is willing to consider setting up an R&D team in Japan to develop a long-term roadmap. Additionally, Imec and Rapidus will consider further collaboration with the upcoming Frontier Semiconductor Technology Center (LSTC), according to METI.

The LSTC is reported to be a technology center incubated after the U.S. and Japan agreed on basic principles for semiconductor cooperation at the first meeting of the Japan-U.S. Commercial and Industrial Partnership (JUCIP) in May. LSTC plans to serve as a research and development base, while Rapidus will serve as a mass production base.

According to Nikkei, Koike said Rapidus would not seek to catch up with TSMC and Samsung in terms of production scale, but would instead explore a different business model focused on rapid production.

According to the METI document, Rapidus will acquire the basic technology of the 2nm process in fiscal year 2022 and start installing EUV lithography equipment, formulate the specifications of the equipment, transmission system and production management system required for a short turnaround time (TAT) production system, and deploy Initial design of the test line.

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In the third-quarter financial report announcement on October 19, ASML stated: “In the EUV High-NA business, ASML received additional orders for TWINSCAN EXE:5200; all current EUV customers have submitted High-NA orders.” The High-NA EUV device is a device that increases the lens numerical aperture (NA) of the light-gathering capability from 0.33 to 0.55. Process finer semiconductor circuits than existing EUV equipment. Most people in the industry believe that High-NA devices are critical to the 2nm process.

According to etnews reports, Samsung Electronics and SK Hynix ordered the next-generation semiconductor equipment High-NA extreme ultraviolet (EUV) exposure equipment from the lithography giant ASML. Following TSMC and Intel, South Korean semiconductor manufacturers are also preparing to introduce equipment capable of implementing the 2nm process. Competition for state-of-the-art processes is expected to intensify.

High-NA EUV equipment is more expensive than currently used EUV equipment, but it can achieve ultra-fine processes (single patterning) in one go, which can greatly improve productivity. As far as Samsung Electronics is concerned, it is necessary to preemptively secure High-NA EUV equipment for 2nm mass production after 3nm mass production. Existing EUV equipment is estimated to cost 200 billion won (about 1.008 billion yuan) to 300 billion won (about 1.512 billion yuan), while High-NA EUV equipment is estimated to cost 500 billion won (about 2.52 billion CNY).

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