TheLec reported that Samsung is planning to use a technology called Backside Power Supply Network (BSPDN) to develop 2nm, which was actually just last week by researcher Park Byung-jae at Samsung. A new technology introduced at SEDEX 2022.
In a nutshell, this approach gives an alternative to process indentation and 3D packaging: developing the backside of the wafer.
In the foundry market, technology is evolving from high-k metal gate planar FETs to FinFETs to MBCFETs and now BSPDNs, Park said.
The FinFET (called 3D transistor in the past) mainly used at this stage is the key chip design technology in the development of the 10nm process. Reduce leakage (electron leakage), but the development of 5nm or even 3nm process means that FinFET will be outdated, so the industry has developed a four-sided all-gate or GAA technology.
The factory then added what it calls nanosheets instead of nanowires to this, and dubbed the technology MBCFETs. But BSPDN here is different and can be understood as an evolution of the chiplet design used by Samsung, Intel and TSMC.
With the chiplet technology solution, we can apply the same process on a single chip, or connect various chips manufactured by different processes from different foundries. This is also the technical solution adopted by Intel’s 14th-generation Core and AMD Ryzen. It is also called For 3D-SoC, logic circuits and memory modules can be combined together at the same time.
According to reports, BSPDN is different from the front-end power supply network, which mainly uses the back-end; the front will have logic functions, while the back will be used for power supply or signal routing.
The concept of BSPDN was first proposed at IMEC in 2019, when a 2nm paper citing the technology was also published at IEDM in 2021.
In this Korean paper titled “SRAM Macro and Logic Design and Optimization Using 2nm Process Back-End Interconnection”, the author proposes to move functions such as the power supply network to the back of the chip to solve the problem of wiring congestion caused by using only the front side. Compared to FSPDN, BSPDN is said to provide 44% better performance while 30% more power efficient.
Eric Beyne, Senior Fellow, Vice President of R&D and Program Director of 3D Systems Integration at Imec, said: “A chiplet involves a chiplet that is individually designed and processed. A well-known example is high-bandwidth memory (HBM) – also known as dynamic random access. A stack of memory (DRAM) chips. This memory stack is connected to the processor chip through an interface bus, which limits their use to latency-tolerant applications. As a result, the chiplet concept will never allow the fast access to and from mid-level cache memory.”
With 3D-SOC integration, we can implement logical partitioning of memory using direct and shorter interconnects, resulting in significantly improved performance. In the paper, the authors show an optimized implementation of a 3D-SOC design with the memory macros at the top of the die and the rest of the logic at the bottom of the die—a full 40% increase in operating frequency compared to the 2D design.
One possible partition of a high-performance 3D-SOC system involves placing some or all of the memory macros at the top of the die and logic at the bottom of the die.
On the technical side, this can be achieved by bonding the active front side of the “logic wafer” to the active front side of the “memory wafer” using low temperature wafer-to-wafer bonding. In this configuration, the original backsides of both wafers are now outside the 3D-SOC system.
Eric Beyne said: “We can now consider utilizing the ‘free’ backside of these chips for signal routing or directly powering transistors in the ‘logic wafer’. Traditionally, signal routing and power delivery have occurred on the front side of the wafer, where they are Competing for space in complex back-end interconnect schemes. In these designs, the backside of the silicon is used only as a carrier. In 2019, Arm’s simulations showed for the first time the beneficial effects of using BSPDN in a CPU) design implemented by imec Developed 3nm process. In this design, the interconnect metal on the backside of the wafer thinning is connected to the 3nm transistors on the front side of the silicon wafer using through-silicon vias (TSVs) on buried power rails.
Therefore, additional performance gains can be expected when BSPDN is implemented to provide power-hungry core logic circuitry at the bottom of a “logic memory” 3D-SOC. Alternative 3D-SOC partitions can also be considered, where some memory blocks, such as L1-level cache static random access memory (SRAM), are also in the bottom die, also powered from the backside.
In addition to expanding the possibilities of 3D-SOC designs, BSPDN has also been proposed for monolithic single-chip logic and SRAM system-on-chip (SOC), which can aid further device and IC expansion.
Geert Van der Plas, project manager at imec, said: “Moving the power supply network to the backside of the silicon has proven to be an interesting approach to solve the back-of-the-line (BEOL) routing congestion challenges and reduce IR drop. This is similar to the 3D-SOC approach. The main difference is that the dummy wafer is now bonded to the target wafer for backside wafer thinning and metallization.” One of imec’s partners announced at the time that it would be implemented in one of its future node chips Such a BSPDN concept.
