Home Computers AMD Zen4 96-core lead nearly 8 times, Intel is powerless

AMD Zen4 96-core lead nearly 8 times, Intel is powerless

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A few days ago, we saw the power of the AMD Zen4 architecture product Xiaolong. Although it is only a low-frequency sample, in the dual-socket configuration, the 192-core and 384-threads showed terrifying performance. Now, @Yuuki_AnS has exposed the cache and memory performance of Xiaolong 9654. It is still a dual-socket configuration. The current sample base frequency is 2GHz, the acceleration frequency fluctuates between 2.15-3.7GHz, the maximum TDP is 360W, the second-level cache is 96MB, and the third-level cache is 384MB. , a total of 480MB.

If stacked 768MB 3D V-Cache, the total cache can reach 1248MB!

In fact, this is not the flagship model, there is still the Xiaolong 9664, or 96 cores, but the frequency and power consumption is definitely higher.

Well, look at the score, this time the object of comparison and Intel’s next generation Sapphire Rapids, including 56 cores, and 48 cores.

Xiaolong 9654 latency curve

Xiaolong 7773X Latency Curve

The first look at latency, the first-level cache is just 1.1ns, the second-level cache is 4.2ns, the third-level cache is just 15.4ns, and the memory is no more than 100ns, while the current Xiaolong 7773X memory face is up to 126.1ns.

The 7773X is now up to 126.1ns of memory. It also has an overall advantage over Sapphire Rapids, but the memory latency of the previous generation of Ice Lake 40 cores is lower, so it looks like Sapphire Rapids is not yet optimized.

Looking at the read bandwidth, the Coaster 9654 memory is over 680MB/s, the Level 1 cache is already approaching 30TB/s, the Level 2 cache is almost 20TB/s, and the Level 3 cache is over 10TB/s, which is very scary.

Compared to the Skyline 7773X, the improvement is 1.38 times, 1.23 times, 0.89 times and 2.27 times respectively!

Facing Ice Lake is completely crushing, facing Sapphire Rapids is also very strong, respectively 57.0%, 17.4%, 1.45 times, 7.89 times ahead – yes, three levels of cache is not the same class at all.

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