According to some early reports, the Google Tensor G3 chip will be co-designed with Samsung’s System LSI arm and manufactured using Samsung’s 4nm process. Some new information claims that starting with the Tensor G4, Google can design its chips completely in-house and manufacture them using TSMC’s 4nm process. For Tensor G5, Google can use TSMC’s 3nm process to manufacture.

However, there are some reports that although Google hopes to switch to TSMC’s 4nm process for Tensor G4, the cost is too high for Pixel, so Google will eventually turn to Samsung’s foundry, but the news did not specify what process Tensor G4 uses (Samsung The foundry previously launched the 3nm GAA process).

Revegnus broke the news that the Tensor G3 chip will adopt the “1+4+4” nine-core design. The attached information is as follows:

 1 x 3.30GHz Cortex-X3 core

 Four 2.60GHz Cortex-A715 cores

 Four 2.20GHz-2.30GHz Cortex-A510 cores

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He said that by 2026, the global 3nm process node foundry market will reach US$24.2 billion, an increase of more than 20 times from this year’s US$1.2 billion.

At present, Samsung Electronics is the only company that has announced the successful mass production of 3nm chips. As major semiconductor manufacturers such as Samsung Electronics, TSMC, and Intel begin to introduce EUV equipment and process technology continues to develop, it is expected that the 3nm process will become a key competitive node.

According to Gartner data, as of the end of this year, the 5nm and 7nm processes accounted for the largest share in the foundry market, with a market size of 36.9 billion US dollars, and their share will be gradually replaced by 3nm in the future. “With the launch of the 14nm FinFET process, Samsung Electronics has risen to No. 2 in the foundry market,” he said.

It is said that the 3nm node requires a new device structure to improve performance. Samsung, which is the first to achieve mass production of the 3nm process, uses MBCFET technology with a gate-around (GAA) transistor structure, which has significantly improved performance and power consumption compared with FinFET.

“In the case of FinFETs, performance increases with pin count, but power dissipation increases more than performance,” he said. “MBCFETs, on the other hand, are much more efficient because they operate on similar improved performance and power at the same level.”

Specifically, in FinFET technology, the performance is increased by 1.3 times, but the power consumption will also be increased by 2.2 times. In MBCFET, when the performance is increased by 1.7 times, the power consumption will only increase by 1.6 times, which is relatively more efficient.

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To be able to tackle these plans it has and better serves its customers, Samsung will upscale its production by up to three times. With the dependency of more industries on chips, there is a need to put more effort into the production process. Among the steps that Samsung will take to upscale its production are; foundry process technology innovation, process technology optimization for each specific application, stable production capabilities and customized services for customers.

Read also: Samsung Galaxy S23 series will launch a bit earlier than expected.

Achieving its goal to roll out the 2nm process and the 1.4nm process by 2025 and 2027 respectively is not far from the reach of Samsung Foundry. Considering that the industry got the first supply of 3nm chips from Samsung, we can say that they are more than capable of stepping up production to meet the industry’s future needs. Delving deeper into process technology optimization, Samsung will build the 2.5D/3D heterogeneous integration packaging technology for foundry service.

This packaging technology will bring forth a 3D packaging X-Cube with micro-bump interconnection in the year 2024. Following this will be the bump-less X-Cube, which will be available just two years after the micro-bump interconnection. To better achieve this, Samsung Foundry will diversify its workforce in various regions with a focus on different industries.

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Such improvements this new process will bring will affect the overall power efficiency and performance. President and Head of Samsung Foundry business, Dr Siyoung Choi, is optimistic about this project. According to him, Samsung will maintain its leadership in the semiconductor manufacturing business. 

In comparison with the available 5nm chips, the new 3nm process will offer some real upgrades. These upgrades include a 23% improvement in performance and a 45% power consumption reduction. It also reduces the surface area of chips by up to 16%. Well, these records speak for the first-generation 3nm fabrication process. 

The second-generation 3nm process takes these upgrades even further in comparison with the 5nm process. Power consumption goes down by 50%, performance goes up 30%, and surface area reduces by 35%. Both first and second-generation 3nm processes will shrink the transistor while maintaining a good flow of current. 

Mass production of the 3nm fabrication process from Samsung Foundry is already in motion. This puts Samsung ahead of TSMC in the 3nm tussle. By next year, we will begin to see processor chips use the 3nm process with performance upgrades.

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