Officially, Micron LPDDR5X has a capacity of up to 16 GB, the highest performance and lowest power consumption in the industry.

An introduction to Micron’s 9.6 Gbps LPDDR5X memory as follows:

The new memory has a speed level of up to 9.6 Gbps and a peak bandwidth that is more than 12% higher than the previous generation. It is built on Micron’s industry-leading 1β process node and provides the industry’s most advanced energy-saving features. With the support of dynamic voltage and frequency scaling core technologies, the power consumption is reduced. Reduced by nearly 30%.

“By bringing the power of large language models to flagship phones, generative AI has the potential to unlock unprecedented productivity, ease of use and personalization for smartphone users,” said Mark Montierth, vice president and general manager of Micron’s Mobile Business Unit. Micron’s 1β LPDDR5X, combined with the Qualcomm Snapdragon 8 Gen 3 mobile platform, provides smartphone manufacturers with improved performance and energy efficiency that are critical to enabling revolutionary AI technologies at the edge.”

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Micron’s 7500 series products utilize 232-layer 3D NAND flash memory. Micron also mentioned that this is the world’s first mainstream data center SSD based on 200+ layers of NAND flash. CK Storage has previously launched consumer-grade products using 232 layers of 3D NAND.

The series of SSDs are described as having a 6×9 QoS latency of less than 1ms, with maximum sequential read speeds of 7GB/s, 5.9GB/s writes (97% higher than the competition), and maximum random reads of 1100K IOPS (13% higher) and writes of 410K IOPS (242% higher).

Thanks to the low latency feature, the drive’s random read latency is approximately 83% lower than the competition’s at 100% read workloads, and random mixed I/O latency is approximately 82% lower than the competition’s at 70% read/30% write workloads.

Micron said the 7500 SSDs are designed to meet the needs of storage-intensive data center workloads such as artificial intelligence, database, content delivery, real-time analytics, social media platforms, cloud computing and virtualization scenarios.

The SSD series is compliant with the TCG Opan 2.01 specification, is SPDM 1.2 certified, and utilizes AES-256-based hardware data encryption.

In addition, Micron’s 232-layer 3D TLC NAND flash chips utilize the CuA architecture, which uses string-stacking technology for NAND, a new technology that significantly reduces the die size of NAND flash, helping to lower costs.

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Micron’s demonstrated 1β DDR5 DRAM is now available to data center and PC users and can reach peak speeds of 7200 MT/s.

Featuring advanced high-k CMOS device technology, 4-phase clocking and clock-sync1, this new DDR5 memory delivers a 50% performance improvement over the previous generation and a 33% improvement in performance per watt.

The new 1β DDR5 DRAM product line offers module densities from 4,800 MT/s to 7,200 MT/s to meet the needs of data center and client applications.

Brian Callaway, corporate vice president of Micron’s Core Computing Design Engineering Group, emphasized the importance of this development, stating, “The high-volume production and availability of 1β DDR5 DRAM for client and data center platforms marks a significant milestone for the industry. Our collaboration with ecosystem partners and customers will drive faster adoption of these high-performance memory products.”

Micron’s 1β technology supports a broad portfolio of memory-based solutions, including DDR5 RDIMMs and MCRDIMMs using 16Gb, 24Gb and 32Gb DRAM chips, LPDDR5X, HBM3E and GDDR7 using 16Gb and 24Gb DRAM chips, with the 16Gb DDR5 memory products to be sold through both direct and channel partner Sales.

After industry analyst TechInsights disassembled the iPhone 15 Pro, it found that Micron’s latest ultra-high-density D1β (D1b) LPDDR5 16 Gb DRAM chips were used inside, marking the industry’s first foray into D1β.

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Just over a year ago, Micron announced plans to invest approximately US$15 billion by the end of this century to build a new factory for cutting-edge memory manufacturing. ISI’s R&D center is located at the same location. Over the life of the project, Micron will directly inject $15.3 billion into the Idaho economy, including $13 billion in direct payments to Idaho businesses. The project will create more than 17,000 new jobs in Idaho, including 2,000 direct Micron jobs, further meeting the need for a diverse, highly skilled workforce.

Boise is home to Micron’s corporate headquarters, a newly expanded Center of Excellence for Technology Innovation, and North America’s only DRAM R&D and manufacturing facility. Nearly two-thirds of Micron’s patents come from Boise team members, more than three patents a day.

Clean room space at the new fab is expected to come online in phases starting in 2025, and DRAM production will continue to increase in the second half of the decade as industry demand grows. Ultimately, the cleanroom space will be 600,000 square feet, equivalent to the size of 10 U.S. football fields, making it the largest single cleanroom ever built in the United States when completed.

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It is learned from reports that Micron plans to start mass-producing complex memory chips using the 1γ process (third-generation 10-nanometer node) that relies on extreme ultraviolet (EUV) lithography by 2026, so the company needs to obtain funds as soon as possible. .

Japan’s Ministry of Economy, Trade and Industry’s massive two-year budget of 2 trillion yen ($13.385 billion) is explicitly earmarked for subsidies related to semiconductor investment. Among them, TSMC’s Kumamoto factory received up to 476 billion yen ($3.1857 billion) in funding, and the cooperation between Kioxia and Western Digital was supported by subsidies worth 92.9 billion yen ($621 million).

The huge capital infusion into semiconductor companies underscores Japan’s commitment to reducing its reliance on overseas chip suppliers and rebuilding its domestic semiconductor industry. Japan aims to avoid potential risks associated with disruptions to international supply chains by strengthening domestic capabilities to ensure smooth and robust internal supply of key technology components.

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GAAP net loss for the fourth quarter was approximately $1.43 billion (currently approximately RMB 10.439 billion), compared to net income of $1.49 billion for the same period last fiscal year; diluted loss per share was $1.31; and cash flow from operations was $249 million, compared to $24 million in the prior quarter and $3.78 billion in the same period last fiscal year.

For the full fiscal year 2023, Micron reported revenue of $15.54 billion (currently approximately RMB113.442 billion), compared to $30.76 billion in the prior year; GAAP net loss of $5.83 billion (currently approximately RMB42.559 billion), or $5.34 per diluted share; non-GAAP net loss of $4.86 billion, or $4.45 per diluted share; and operating cash flow of $1.56 billion. Non-GAAP net loss of $4.86 billion, or $4.45 per diluted share; and operating cash flow of $1.56 billion, compared to $15.18 billion in the prior year.

Sanjay Mehrotra, president and chief executive officer of Micron Technology, said, “In fiscal 2023, Micron acted decisively on supply and cost in a challenging environment for the memory and storage industry. With increased demand and tight supply, our 2023 results set us up well for a market recovery in 2024. As AI surges from the data center to the edge, we look forward to setting industry TAM revenue records in 2025.”

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Micron’s 32 Gb DDR5 chips reportedly utilize the company’s 1 beta (1-beta) manufacturing process, and no official information on their speed or power consumption has been disclosed at this time. 32Gb DDR5 chips pave the way for a single 128 GB memory stick for servers, and make it possible to produce memory modules with 1 TB capacity,

Samsung announced on September 1 this year that it had developed its largest capacity 32Gb DDR5 DRAM using 12-nanometer (nm) level process technology, which allows it to develop solutions to realize 1TB memory modules. In terms of power consumption, a 128GB memory module packaged with Samsung’s 32Gb DDR5 chips consumes approximately 10% less power than the previous generation. Mass production of Samsung’s new 12nm-class 32Gb DDR5 DRAM is scheduled to begin by the end of this year.

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Micron’s HBM3E memory uses an eight-tier layout with 24 GB per stack, and is produced using 1β technology for excellent performance.

Micron said its HBM3E memory will offer the same level of performance as its competitors, but at a lower cost than other competitors. Micron said it will begin commercial shipments next year and is currently seeking certification for these products to meet NVIDIA’s requirements.

HBM (High Bandwidth Memory) is a vertically connected multiple DRAMs that can significantly increase data processing speeds. HBM DRAM products are developed in the order of HBM (first generation), HBM2 (second generation), HBM2E (third generation), HBM3 (fourth generation), and HBM3E (fifth generation). hbm3e is the HBM3E is an extended version of HBM3.

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Tata Projects (a subsidiary of the Tata Group) announced on Saturday that it will work with Micron Technology to build an advanced semiconductor assembly and testing plant in Sanand, Gujarat. According to reports, the first phase of the plant will start soon and is expected to be commissioned by the end of 2024.

According to public information, the factory is located in Gujarat Industrial Development Corporation area in Sanandi, Gujarat, covering 93 acres of land, and the total investment will reach 2.75 billion U.S. dollars (Currently, about RMB 20.075 billion), of which Micron invested up to 825 million U.S. dollars (currently about 6.023 billion yuan), and the rest will be provided by the central government of India and the state government.

A Tata statement said, “This enduring project is an important milestone for us and the largest investment under the India Semiconductor Mission (ISM).”

The first phase of the plant’s construction will reportedly include a 500,000-square-foot cleanroom space, which is scheduled to be operational by the end of 2024. In addition, the project includes the design and construction of India’s first DRAM and NAND assembly and test facility.

Tata Projects also plans to use modern construction methods and an EPC delivery approach that accelerates construction integration through 4D BIM and hybrid modularization. According to the statement, the Sannadi facility will be designed in accordance with the Green Building Council’s LEED Gold standard and will also incorporate advanced water conservation technologies.

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The minister said Micron’s investment in India has spurred a change of attitude among those on the fence; therefore, it is in the government’s interest to ensure that the company’s first factory becomes operational as soon as possible.

Micron CEO Sanjay Mehrotra said at Semicon India 2023 in July this year that the semiconductor and packaging giant will begin the next phase of expansion after 2025.

The company has previously announced an investment of US$800 million to set up a semiconductor assembly, testing, marking and packaging (ATMP) factory in Sanad, Gujarat, India. Indian officials say more such facilities will come up after the first plant becomes operational.

“Two major benefits will come from the success of Micron’s first investment in India, one is that it will serve as a guide for other companies and investments coming to Doleira or elsewhere, and two is that those companies that come to India will see an increase in value,” said Chandrasekhar. , which can be further expanded.”

He also mentioned: “We have created a policy framework and attracted a globally important company. They will start with packaging and are expected to enter the semiconductor manufacturing field in the next four to five years. The Indian government is talking to all entities in the semiconductor market, the level of participation in discussions has increased significantly compared to entities that were previously less focused on India.”

He added that fabs, including packaging, usually appear in large numbers in a certain region, citing Malaysia and Japan as examples. “If you look at the history of the development of fabs and packaging fabs anywhere in the world, ( You will find that) they all started with just one development. Unless the local environment or government policies change extremely badly, they are all expanding into large-scale complexes with multiple factories, multiple fabs, and multiple packaging plants.

At present, the Indian government has provided financial assistance of approximately US$1.95 billion to Micron, and the total investment in the project has reached US$2.75 billion. Construction of the facility is expected to begin this year, with the first phase expected to be operational by the end of 2024, and India expects its first locally produced chips to be available in December 2024.

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