According to reports, in order to develop its own automotive semiconductors, Hyundai Motor established a semiconductor development laboratory in June last year and hired Kim Jong-sun, an engineer who had worked on the development of automotive chips Exynos Auto at Samsung Electronics’ system LSI division.

Hyundai Motor is planning to select a semiconductor design company for its semiconductor-related business, and the foundry is expected to be Samsung Electronics or TSMC. Currently, Samsung Electronics and TSMC are the only foundries producing automotive chips using the 5-nanometer process.

The semiconductor that Hyundai Motor plans to develop this time is a chip that supports SDV (Note: software-defined vehicle, software-defined vehicle). SDV will use software to control relevant functions of the car, including driving experience, comfort and even safety.

Hyundai aims to apply OTA technology to all vehicles by 2025 and gradually transition to SDV by integrating next-generation common platforms and “feature-centric” architecture.

Industry insiders said that obtaining advanced automotive semiconductors is the key to leading the future mobility market. Hyundai Motor’s decision to develop and equip self-developed chips shows its determination to gain an advantage in competition with global automakers.

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Canon said that the working principle of this production equipment is different from that of industry leader ASML. It is not photolithography, but more similar to printing. It does not use the principle of image projection to transfer the microstructure of the integrated circuit to the silicon wafer.

The equipment can be applied to silicon wafers as small as 14 square millimeters, allowing the production of chips equivalent to the 5nm process.

Canon said it will continue to improve and develop this system and is expected to be used to produce 2nm chips in the future.

Note: Nanoprinted lithography is generally considered a low-cost alternative to optical lithography, and memory chip manufacturers such as SK Hynix and Kioxia have tried to use it in the past. Kioxia had previously conducted tests, but potential customers complained that the product had a high defect rate and ultimately gave up.

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TSMC does not comment on rumors about dynamics related to capacity utilization. According to the data previously disclosed by TSMC, the 5nm and 7nm processes contributed about 50% of the performance in the first quarter of this year, which is the main source of revenue. There is quite positive help.

Industry insiders pointed out that TSMC’s 5nm process has a monthly production capacity of about 130,000 pieces. Previously, the capacity utilization rate was estimated to have dropped to more than 50%, and it has recently begun to heat up. The current monthly production is estimated to be about 90,000 to 100,000 pieces. Converting production capacity utilization The rate has risen to about 70% to 80%, which is faster than the original market expectation, mainly due to the fact that NVIDIA, a major customer, has placed additional orders with TSMC in response to market demand, and the related production should be gradually released from July.

In terms of 7nm process, TSMC’s related capacity utilization rate is not as good as 5nm. The supply chain believes that TSMC’s capacity utilization rate in the first few months before 7nm may be reduced to only 30% to 40%, but it has returned to about 50% level.

In addition, in terms of TSMC’s most advanced 3nm process, industry insiders mentioned that the most important customer is still Apple, which mainly produces the latest A-series processors equipped in the upcoming high-end iPhone 15 new machine. Filming will follow.

TSMC previously stated that because the client’s demand for its 3nm process exceeds its supply capacity, it is expected that the 3nm process will be fully loaded this year and will contribute a large amount of revenue from the third quarter. The N3E process will be mass-produced in the second half of the year.

It is noticed that Liu Deyin, chairman of TSMC, said a few days ago that due to the adjustment period of industrial inventory this year, the company’s performance may show a little negative growth, but the prospects are still very bright, and it is ready for the next wave of good growth next year.

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Amazon announced in 2018 that it will use its own Graviton processor in AWS server hardware, and Google plans to follow up with self-developed chips.

The report pointed out that Google is developing two chips internally, one of which is code-named Cypress, which is completely designed in-house by Google Israel; the other chip is code-named Maple, which is based on Marvell Technology design.

The Cypress chip is considered a “Plan A” processor by Google, while the Maple chip is considered a “Plan B” processor. Both will use the Arm-based 5nm chip process. Other than that, there is no further information on the specifications of the two custom chips.

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A chart of TSMC’s wafer pricing shows that the price jump from 7nm ($10,000) to 5nm ($16,000) wafers is about 60%. Now with 3nm, TSMC’s wafer unit prices are expected to exceed $20,000, which will mean we’re bound to get more expensive next-generation CPU and GPU products.

TSMC’s 3nm wafer pricing is rumored to hit the $20,000 mark, leading to increased costs for next-generation Intel, AMD and NVIDIA CPUs/GPUs. (Image source: DigiTimes)

Currently, AMD and NVIDIA are some of TSMC’s major customers, along with Apple and others. NVIDIA has increased the price of its graphics cards for each market segment. the RTX 4090 is priced 10-15% higher than the RTX 3090 and the RTX 4080 is priced over 50% higher than the RTX 3080. This comes after NVIDIA’s CEO Jen-Hsun Huang also visited Taiwan to discuss with TSMC’s CEO about getting early access to 3nm wafers for their next-generation GPU lineup.

AMD has been able to offset prices by mixing and matching different nodes on its chip offerings. the Ryzen, Radeon and EPYC families utilize both 5nm and 6nm technologies and chips to help reduce the overall costs associated with a single die. Going forward, Intel will also leverage TSMC’s N5 and N3 process nodes to develop Meteor Lake and Arrow Lake tGPU IPs.

However, this dominant situation will also cause the price of each generation of the foundry to rise sharply without any resistance. As production costs rise, the chip industry will inevitably pass them on to downstream customers and consumers, and the prices of new-end products will no longer come back down.

Nvidia CEO Jen-Hsun Huang said bluntly that despite limited performance gains, the increase in new products is justified because the price of 12-inch foundry wafers has increased significantly compared to the past, rather than just being a little more expensive.

But this reliance on TSMC means that the semiconductor manufacturing company will continue to be in a dominant position to offer higher prices for its technological advantage over other companies. Rival Samsung has also said they will start mass production of their own 3nm (GAP) node by 2024, but things are not looking good as yields are less than 20% and there are still many issues to be resolved with Samsung’s next-generation node. All of this means that chip prices will continue to move higher on the cost side, and unless there is another competitor at the same level as TSMC, we can’t expect this pattern to be broken.

Intel has said that allowing chipmakers such as Nvidia and AMD to produce their products in their soon-to-be-built factories is one of their goals, and the new rising force under this old chipmaker is also worth watching.

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In a statement submitted to Android Authority, a Google spokesperson said: “We built Google Tensor G2 specifically for real-world use cases. Our final architecture (including 5nm) helped us achieve this goal while improving performance and Energy efficiency. This approach also enables us to add new capabilities while taking a step forward in machine learning using our next-generation TPU and G2.”

So Tensor G2 is actually a 5nm process chip. However, Google did not tell the exact node process and manufacturer, but it can be confirmed that Samsung is Google’s main partner. On Samsung’s roadmap, there are two 5nm process nodes, the 5LPE used by the original Tensor and the subsequent 5LPP. It’s just that it’s not yet certain which node process Tensor G2 uses.

Either way, given that companies like to tout their use of smaller nodes, Google’s wording makes it clear that the Tensor G2 is not built on what Samsung (or TSMC) calls 4nm, such as the 4LPE nodes used in the Exynos 2200 and Snapdragon 8 Gen1.

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