Home Computers SMART Modular Launches Its First DDR5 XMM CXL Memory Module

SMART Modular Launches Its First DDR5 XMM CXL Memory Module

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SMART Modular Technologies, known for its highly reliable memory solutions, has just launched its first Compute Express Link memory module. By adding cache to the back of the CXL interface, the DDR5 XMM CXL module can further enhance the performance of server/data center applications. By breaking the 8 / 12 channel memory limitations of most servers today, the CXL solution makes it easy to extend the big data processing power of your infrastructure.

The data center industry is said to have opened a whole new era for the memory module industry by choosing CXL, a combinable serially connected memory architecture.

● First, servers can significantly increase capacity and bandwidth beyond the main memory DIMM modules.
● Second, servers with XMM CXL memory modules can dynamically adjust the configuration for different application scenarios and workloads without shutting down.

● Even better, memory can be shared across nodes to meet throughput and latency requirements.

Mike Rubino, Vice President of Engineering at SMART, stated.

SMART has a long history of supporting industry standards such as JEDEC, CCIX / Gen-Z Alliance, and OpenCAPI / OMI.

"Now, we are excited to work more deeply with CPU and CXL ASIC vendors to bring CXL memory solutions that meet demanding bandwidth, capacity and performance requirements."

The new XMM CXL module features an advanced ASIC controller in the E3.S form factor, paired with 64GB of DDR5 memory compliant with the CXL 2.0 specification.

The modules are designed to allow customers to work with CPU partners to build the CXL ecosystem and verify compliance across a variety of server platforms.

SMART is also expected to offer CXL XMM products including AIC add-on cards and E1.S form factors soon to cater to different server chassis configurations and application scenarios.

Finally, in addition to supporting ASIC- and FPGA-based memory module technical expertise, it also meets RAS functional/CXL verification requirements — including features such as data path integrity, poisoning and error injection, and Chipkill ECC — to ensure that new modules work as expected.

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