According to DigiTimes, Samsung Foundry Vice President Jeong Gi-Tae revealed that Samsung will soon launch the SF1.4 (1.4 nm) process, and the number of nanosheets will be increased from 3 to 4. , is expected to significantly improve performance and power consumption.
Samsung is seeking to expand its leading position in the Gate-All-Around (GAA) platform. After launching the GAA-based SF3E, it plans to launch the SF1.4 (1.4nm) process in 2027 to further improve the process by increasing the number of nanosheets.
Increasing the number of nanosheets per transistor increases the drive current, thereby improving performance. More nanosheets allow more current to flow through the transistor, thereby enhancing its switching ability and operating speed.
Additionally, more nanosheets allow for better control of current flow, which helps reduce leakage current and thus lower power consumption. Additionally, improved current control means the transistors generate less heat, improving power efficiency.
It was previously reported that Samsung also plans to use backside power supply (BSPDN) technology in the 1.4nm process to better tap the potential of the space on the back of the wafer, but it has not yet been implemented globally.
Although the semiconductor industry no longer uses gate length and metal half-pitch to systematically name technology nodes, there is no doubt that the current process technology is also more advanced with smaller numbers.
As the semiconductor process shrinkage route continues to advance, the distance between circuits in integrated circuits is also constantly narrowing, causing interference with each other. BSPDN technology can overcome this limitation because we can use wafers to Construct the power supply route on the back to separate the circuit and power space.
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