Rambus has just released a next-generation PCIe 6.0 interface subsystem designed to power next-generation high-performance data center and AI SoC solutions. As an industry-leading supplier of silicon and silicon IP, Rambus is committed to making data faster and more secure. The PCIe Express 6.0 PHY and controller IP, announced today, also includes support for the latest CXL 3.0 connectivity specification.
(Source: Rambus Press Releases)
Scott Houghton, general manager of Rambus Interface IP, said:
"Rapid advances in artificial intelligence (AI)/machine learning (ML) and data-intensive workloads are driving continued evolution in data center architectures, while also placing higher demands on performance levels. The Rambus PCIe 6.0 interface subsystem meets the performance requirements of next-generation data centers with best-in-class latency, power, area and security."
In terms of specifications, the Rambus PCIe 6.0 interface subsystem provides data rates of up to 64 GT/s, complemented by full optimization to meet the needs of advanced heterogeneous computing architectures.
Within the subsystem, the PCIe controller has an Integrity and Data Encryption (IDE) engine dedicated to protecting PCIe links and the valuable data passing through them.
On the PHY side, it also provides full support for CXL 3.0, enabling caching, coherent memory sharing, and chip-level solutions for scaling and pooling.
Additional PCI Express Features:
"● Compatible with PCIe 6.0 (64 GT/s), 5.0 (32 GT/s), 4.0 (16 GT/s), 3.1/3.0 (8 GT/s) and PIPE 6.x (8 / 16 / 32 / 64 / 128-bit) ● PIPE 10b/20b/40b/80b bit width supporting SerDes architecture ● Support original PIPE 8b/16b/32b/64b/128b bit width ● Compliant with PCI-SIG's Single-Root I/O Virtualization (SR-IOV) specification ● Supports multiple virtual channels (VCs) in FLIT/non-FLIT mode ● Support endpoint (Endpoint), root port (Root-Port), dual-mode (Dual-mode), switch port (Switch Port) configuration ● Backwards support from PCIe 6.0 to PCIe 1.0 rates ● Supports Forward Error Correction (FEC) -- a lightweight algorithm with low latency ● Support L0p low power mode ● Up to 4-bit data path parity protection ● Supports clock gating and power gating ● RAS features -- including LTSSM timer overrides, ACK/NAK/Replay/UpdateFC timer overrides, unscrambled PIPE interface access, error injection on Rx and Tx paths, restoration of detailed state, etc., allowing for safe in-mission Deploy IP SoCs reliably."
Shane Rau, research vice president for computing semiconductors at IDC, said:
"PCI Express is ubiquitous in the data center, and CXL is growing in importance as companies pursue ever-escalating speeds and bandwidths to meet the higher performance levels of next-generation applications. Additionally, as more chip companies emerge to support new data center architectures, access to IP solutions for high-performance interfaces will also be key to enabling this ecosystem."
Finally, the Rambus PCIe 6.0 interface subsystem has the following key features:
"● Supports PCIe 6.0 specification, including 64 GT/s data rate and PAM4 signaling. ● Improve link robustness by deploying low-latency forward error correction (FEC) ● Supports fixed FLIT size for high bandwidth efficiency ● Backward compatible with PCIe 5.0, 4.0 and 3.0/3.1"
