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AMD Releases RDNA3 Instruction Set Architecture Documentation

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AMD has now put online the RDNA3 instruction set architecture (ISA) document on the official website, which details the instruction content of the RDNA3 architecture, with 606 pages.

This very complex document is for developers who want specific instructions enabled or modified for the RDNA3 architecture and provides knowledge about the RDNA3 shader code execution model, the memory hierarchy, and lists all available instructions.

The company has only listed one RDNA3 GPU, the Navi 31, for the Radeon RX 7900 series desktop graphics cards.

Navi31: One GCD + four MCD core designs, 12,288 stream processors, 96MB unlimited cache, possible 192MB 3D cache version, 384-bit memory bit width.

Navi32: One GCD + four MCD core designs, 7680 stream processors, 64MB unlimited cache, 256-bit memory bit width.

Navi33: Single-chip design, 4096 stream processors, 32MB unlimited cache, 128-bit memory width.

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