Alphawave said it has taped out one of the industry’s first chips using TSMC’s N3E manufacturing technology (the second-generation 3-nanometer process node). The chip, which has been produced by TSMC and successfully passed all necessary tests, will be showcased at TSMC’s OIP Forum later this week.
The chip is the Alphawave IP ZeusCORE100 1-112Gbps NRZ/PAM4 Serializer-Deserializer (SerDes) that supports a number of standards that will become popular in the coming years, including 800G Ethernet, OIF 112G-CEI, PCIe 6.0 and CXL3.0. SerDes is said to support ultra-long channels, providing a flexible connectivity solution for next-generation servers.
“Alphawave is proud to be one of the first companies to leverage TSMC’s state-of-the-art 3-nanometer technology,” said Tony Pialis, President and CEO of Alphawave Corporation. “Our partnership will continue to bring innovative high-speed connectivity technologies for the most advanced data Center provides power, and we are excited to showcase these solutions at the TSMC OIP Forum event.”
TSMC plans to launch five 3nm-scale process technologies in the next two to three years, the first-generation 3nm process N3 is expected to be used by TSMC’s big customer Apple for a few designs, while the second-generation 3nm process N3E will have an improved process window, This means faster throughput times, higher yields, higher performance and lower power consumption.
N3E is expected to be more widely adopted than N3, but its mass production is scheduled to begin in mid-2023 or Q3 2023, about a year after TSMC starts high-volume manufacturing (HVM) using its N3 production node.
After TSMC starts N3E HVM next year, it plans to offer three more 3-nanometer nodes, including performance-oriented N3P, N3S for chips requiring high transistor density, and performance-demanding applications. N3X, such as microprocessors.
