TSMC research general Dr. Yu-Chieh Mi has revealed that TSMC will acquire ASML next-generation extreme ultraviolet micro-imaging equipment (high-NA EUV) in 2024 to develop related infrastructure and architectural solutions for customers.
TSMC’s Vice President of Business Development, Xiaoqiang Zhang, has previously stated that after acquiring the equipment, it will initially be used mainly for joint research with partners.
From the previously announced information, the unit price of the High-NA EUV lithography equipment is estimated to be $400 million (about RMB 2.8 billion), which is two to three times more than the existing EUV lithography equipment.
Samsung Electronics Vice Chairman Lee Jae-yong previously held talks with ASML about introducing the Dutch semiconductor equipment maker’s next-generation extreme ultraviolet (EUV) lithography equipment and reached an agreement to introduce EUV lithography equipment for this year’s production and high-numerical aperture (High-NA) EUV lithography equipment planned for next year.
Earlier this year, Intel also announced that it had signed a contract to purchase five such devices (TWINSCAN NXE:3600D) for the production of 1.8-nanometer chips in 2025. TSMC also said at the Silicon Valley Technology Symposium on June 16 that it will bring High-NA EUV lithography equipment to its process for the first time in the world in 2024.
For now, advanced lithography is the key factor to measure the upper limit of chip manufacturing, and this High-NA lithography is expected to reduce the size of 66%. And in the field of chip manufacturing, although the current 3nm, 5nm no longer represents the actual gate width, but certainly the smaller the better.
It is said that this new EUV system can achieve 0.55 numerical aperture, compared with the previous EUV system equipped with 0.33 numerical aperture lens (TWINSCAN NXE:3400B and NXE:3400C), the accuracy will be improved, and can achieve higher resolution patterning.
It is reported that the current cost of each ASML machine is up to $160 million, and major chip makers are planning to invest more than $100 billion in additional manufacturing plants in the next few years to meet further semiconductor demand.
Officials have revealed that the High-NA machines will be 30 percent larger than existing machines, which were already so unimaginably large that three Boeing 747s were needed to load them.
TSMC previously announced that it aims to mass produce its N2 process in 2025, and unlike the 3nm process node, the 2nm process node will use Gate-all-around FETs (GAAFET) transistors, which TSMC says will provide a 10 to 15 percent performance improvement over the 3nm process and also reduce power consumption by 25 to 30 percent. The N2 process is expected to be ready for risky production by the end of 2024 and to enter high-volume production by the end of 2025, with customers receiving their first chips in 2026.