In the United States, TSMC held the North American Technology Forum in Santa Clara, California, USA, and announced the latest progress and roadmap of its 3nm process. Among them, the most interesting is the N3X process, which will be put into mass production in 2025, providing the strongest chip manufacturing capabilities for the high-performance computing (HPC) field.
According to official information from TSMC, TSMC’s 3nm process family includes four versions, namely the basic N3, the cost-optimized N3E, the performance-enhanced N3P, and the high-voltage tolerant N3X. Among them, N3E and N3P are optically scaled down versions based on N3, which can reduce complexity and cost while increasing performance and transistor density. N3X is a process specially designed for the HPC field, which can support higher voltage and frequency to achieve stronger computing power.
According to TSMC, compared with the 5nm process, N3E can reduce power consumption by 32% at the same frequency, or improve performance by 18% at the same power consumption. Compared with N3E, N3P can improve performance by 5% at the same power consumption, or reduce power consumption by 5%~10% at the same frequency. At the same time, N3P can also increase transistor density by 4%, reaching a level of 1.7 times that of the 5nm process.
The N3X is the most powerful version of TSMC’s 3nm process family. It can improve performance by 5% compared to N3P at the same power consumption, reaching a voltage level above 1.2 volts. This is very extreme for a 3nm-level process, and it also means that there will be high power consumption and heat generation problems. Therefore, this process is only suitable for processors that require extreme performance at the HPC level, and requires chip designers to take effective measures to control temperature and power consumption.
TSMC said that N3E will start mass production in the second half of 2023, while N3P and N3X will go into mass production in the second half of 2024 and 2025, respectively. These processes will use the FinFET structure, which is the metal oxide semiconductor field effect transistor (MOSFET) structure. This structure has been used by TSMC for many years, and it has mature and stable characteristics.
However, below the 2nm level, TSMC will adopt a new GAAFET structure, which is a Gate-All-Around FET structure. This structure can further increase transistor density and performance, and reduce power consumption and leakage. According to TSMC, the 2nm process is progressing well in terms of yield and component performance and will be mass-produced in 2025 as scheduled. According to TSMC, compared with N3E process technology, 2nm can increase the speed by up to 15% at the same power consumption; at the same speed, the power consumption can be reduced by up to 30%, while the chip density increases by more than 15%.
