Supported by the European Space Agency, the Occamy processor developed by engineers from the Federal Institute of Technology in Zurich and the University of Bologna is now tape-out. It uses two chiplets with 216 32-bit RISC-V cores, an unknown number of 64-bit FPUs, and two 16GB HBM2e memory chips from Micron.
The cores of this processor are interconnected through an interposer, and the dual CPU can provide 0.75 FP64 TFLOPS performance and 6 FP8 TFLOPS computing power.
Neither ESA nor its development partners have disclosed Occamy’s power consumption, but the chip is said to be passively cooled, meaning it could be a low-power processor.
One of the advantages of the chiplet design is that it can subsequently add other chiplets to the package to accelerate certain workloads when needed. There are 216 RISC-V cores and an FPU for matrix operations in each Occamy chip, with a total of about 1 billion transistors distributed on this 73mm2 small chip, based on GF 14LPP.
For comparison, the Intel Alder Lake die measures 163 mm2. In terms of performance, the Nvidia A30 GPU has 24GB of HBM2 memory and can deliver 5.2 FP64/10.3 FP64 Tensor TFLOPS and 330/660 (sparseness) INT8 TOPS.
It is learned that the Occamy CPU was developed primarily as part of the European Space Agency’s EuPilot program, and it is one of many chips that ESA is considering for aerospace computing.
According to reports, Occamy can perform simulation operations on FPGAs, and the implementation has been tested on two AMD Xilinx Virtex UltraScale+ HBM FPGAs and a Virtex UltraScale+ VCU1525 FPGA.
