“While we are working hard to improve the situation, including sending experienced technicians from Taiwan to train local technicians for a short period of time, we expect the production schedule for N4 process technology to be delayed until 2025,” said Liu Deyin, chairman of TSMC.

TSMC, the world’s largest contract semiconductor manufacturer, first announced plans to build a factory in the United States in 2020. In 2022, the company announced that it will invest 40 billion U.S. dollars in Arizona to build two factories. At the time, the first plant was expected to start production in 2024 and the second in 2026. In the future, up to six more factories could be built on the site. In 2022, due to pressure from Apple, TSMC will also transfer its first fab from 5nm to the more advanced 4nm process, and the second fab will support the 3nm process.

When fully operational, the two new fabs are expected to be able to produce approximately 600,000 wafers per year. TSMC will still manufacture most of its state-of-the-art processors in Taiwan, though, and will continue to do so even after the U.S. factory is fully built.

This month, TSMC announced its second-quarter financial report, with net profit down 23% year-on-year, the company’s first quarterly profit decline since 2019. “We believe TSMC has strong growth prospects in 2024. We believe a delay in U.S. expansion is also expected by investors,” Goldman Sachs said in a research note.

As for the other factory in Japan, Liu Deyin said that its progress remains unchanged, and mass production will continue at the end of 2024 according to the established plan. The factory will be used to produce 16nm, 22nm, and 28nm process semiconductors.

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TSMC Chairman Liu Deyin and President Wei Zhejia reviewed the development of TSMC in the past year in the business report to shareholders, and mentioned that TSMC’s technological development is preparing for the 2nm technology (N2), which is expected to start mass production in 2025. Technology will be produced in Hsinchu and Taichung Science Parks.

In terms of technology development, TSMC’s business report to shareholders stated that the company’s 2nm technology will use a nanosheet (Nanosheet) transistor structure and provide full-process performance and power efficiency benefits. Compared with N3E, N2 is 10%-15% faster at the same power consumption, or 25%-30% lower power consumption at the same speed, to meet the increasing demand for energy-saving computing.

TSMC also stated that the research and development of N2 technology is proceeding as planned, and it is expected to start trial production in 2024 and mass production in 2025.

The report also stated that TSMC will increase its research and development expenses to US$5.47 billion in 2022, and the 5nm family technology has entered the third year of mass production, contributing 26% to TSMC’s revenue. %.

The N4 process will start volume production in 2022. TSMC has also launched the N4P and N4X processes. The development of N4P is progressing smoothly and is expected to be mass-produced in 2023; N4X is TSMC’s first technology focused on high-performance computing (HPC) and high workloads and is expected to be designed by customers in 2023 finalized.

Following the mass production of the N3 process in 2022, N3E with better performance, power consumption and yield is expected to be mass-produced in the second half of 2023. TSMC said that N3 and N3E have very high customer participation, and the number of finalized product designs in the first and second years of mass production will be more than twice that of N5, and it is expected that the N3 family will become another large-scale and long-term demand for TSMC. process technology.

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The report pointed out that the N4 and N5 process costs of TSMC’s U.S. plant are about 20% to 30% higher; TSMC’s Kumamoto plant in Japan produces chips on the N28/N22 and N16/N12 nodes that are 10% to 15% higher.

TSMC plans to pass on the high cost of manufacturing fabs in the U.S. and Japan to customers so that it can maintain its 53% gross margin target.

U.S. customers, including AMD and Nvidia, are continuing to negotiate with TSMC and may shift some orders to the Samsung foundry to balance their budgets.

It is learned from the report that Nvidia will use Intel’s 18A and 20A technologies to manufacture chips in addition to Samsung’s foundry. However, as chip designs become more complex and costly, it will be difficult for chip design companies to order similar chips from TSMC and Samsung at the same time.

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According to foreign tech media WccFtech, user @xinoassassin1 has shared a chart of the Phoenix ES APU clock frequency runs.

The chart does not provide details of the SKUs, but only shows a 6-core configuration with 2+4. There are 2 Zen 4 performance cores and 4 Zen 4c efficiency cores.

Core 0 and Core 5 are performance cores clocked between 4.0 – 5.0 GHz with an average of 4.2 – 4.3 GHz. The other 4 efficiency cores run in the 2.5 – 4.0 GHz range, with an average clock frequency of just under 3.0GHz.

It was previously reported that AMD’s “hybrid structure” processor corresponds to the Phoenix 2 mobile APU, adopts TSMC’s N4 process, has 2 performance cores and 4 efficiency cores, is equipped with 4CU RNDA3 core display, and consumes 15-28W. Products such as thin and light notebooks or game consoles. The flagship model of this series of processors is expected to be the R7 7740U, which is one bit lower than the full-core R7 7840U.

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As shown above, AMD’s “hybrid architecture” processors use the terms “Performance Core” and “Efficiency Core” like Intel does. ” terminology.

According to the news, AMD “hybrid architecture” processor corresponds to Phoenix 2 mobile APU, using TSMC N4 process, with 2 performance cores and 4 efficiency cores, equipped with 4CU RNDA3 core graphics, 15-28W power consumption, for products such as thin and light notebooks or gaming handhelds. The flagship model of the processor series is expected to be the R7 7740U, which is one position lower than the R7 7840U with all large cores.

At the moment, AMD has not announced when to release this series of “small and large core” processors.

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