Source: Angstronomics

According to reports, Navi 31 uses a new chip design with a built-in GCD (graphics) core and six MCD (cache) cores. The size of the GPU is estimated to be about 533 square millimeters.

According to rumors, Navi 31 uses a 5nm process, with up to 12288 stream processors and 96MB of infinite cache. Supports a 384-bit memory bus and up to 24GB of GDDR6 memory.

The latest news said that AMD will launch two flagship models this time, with the suffixes XTX and XT, and the video memory is 24GB and 20GB respectively. Both graphics cards will be based on AMD’s 5nm RDNA3 architecture Navi 31 GPU, the XTX model has a 12288 stream processor with 24GB 384bit 20Gbps GDDR6 video memory, and the XT model has a 10752 stream processor with 20GB 320Bit 20Gbps GDDR6 video memory.

The post AMD’s new-gen GPU Navi 31 appearance exposure: 1 GCD + 6 MCD design appeared first on TechGoing.

Navi31

One GCD + four MCD core design, 12288 stream processors, 96MB unlimited cache, 192MB 3D cache version possible, 384 bit memory bit width.

Navi32

One GCD + four MCD core design, 7680 stream processors, 64MB unlimited cache, 256-bit memory bit width.

Navi33

Single chip design, 4096 stream processors, 32MB unlimited cache, 128-bit memory bit width.

According to reports, AMD’s new GPU’s graphics unit GCD uses TSMC’s 5nm process, while the cache unit MCD uses TSMC’s 6nm process. In addition, AMD’s RX 7000 graphics card is reported to have a maximum public version with a triple fan design and dual 8-pin power supply, which may mean that AMD will not use the latest 16-pin graphics card power connector.

The AMD Radeon RX7000 series is now scheduled to launch “later this year” with a 5nm process and RDNA3 architecture in a Chiplet package with a new generation of infinite cache and 50% more power efficiency.

The post AMD RX 7000 graphics card three GPU latest news: respectively 12288 / 7680 / 4096 stream processors appeared first on TechGoing.

Navi 31.

Flagship core, including a GCD graphics unit, six MCD memory control units, the former with an area of 13.1 x 28.2 = 369 square millimeters (margin of error 350-370 square millimeters), and the latter with a single area of 4.68 x 9.36 = 44 square millimeters, for a total area of approximately 633 square millimeters (margin of error 590-630 square millimeters).

Integrated 48 WGP workgroups, 12,288 stream processors, 192MB of infinite cache, with 384-bit 18GHz 24GB GDDR6 memory and a bandwidth of 864GB/s.

Corresponding products are expected to debut in Q4.

Navi 32.

High-end core, including one GCD, four MCD, the former with an area of about 13.1 x 20.1 = 263 square mm, total area of 439 square mm.

Integrated up to 32 WGP workgroups, 8192 stream processors, 128MB of infinite cache, with 256-bit 18GHz 16GB GDDR6 memory and 576GB/s bandwidth.

Navi 31.

Mainstream core, single chip, area 19.5 x 20.5 = 400 square mm.

Integrated up to 16 workgroups, 4096 stream processors, 96-128MB infinite cache, with 128-bit 8GB 18GHz GDDR6 memory with 288GB/s bandwidth.

PS: The above data are currently anecdotal and partly speculative.

The post AMD RX 7000 graphics card three cores of imagination: “very 6 + 1” of the behemoth appeared first on TechGoing.

According to the authoritative exposer @Greymon55, the GCD portion of the Navi 31 core is a little over 350 square millimeters.

This is a full 33% smaller than the 520 square millimeters of the Navi 21 core used in the RX 6900/6800 series, but the latter is a separate core, so it lacks direct comparability.

The area of the Navi 13 MCD section is not known at this time, but six of them would add up to a significant area, and the total area would almost certainly be larger than the Navi 21, or it would not be a separate design.

Assuming 40 square millimeters per MCD, the total area will be 590 square millimeters, almost the same as the NVIDIA AD102 core, which is rumored to be around 600 square millimeters.

Non-equal scale comparison

However, it is worth mentioning that Navi 31 core will eliminate some non-essential and obsolete modules, such as XGMI bus for multi-card parallel connection, GDS (Global Data Sharing), geometry pipeline, scan converter, etc., which can also save a lot of transistors and area.

Also, the Navi 32 core will be a similar small-chip design, with MCDs expected to be reduced to four, and Navi 33 will continue to be a single chip.

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