AMD will launch the EPYC Genoa-X series of server processors with 3D V-Cache this year, with a large 3D V-Cache cache and Zen 4 core, which will support DDR5 memory and PCIe Gen5 and CXL interfaces.

According to information released by Wccftech, the two AMD EPYC Genoa-X CPUs will have similar specifications and both chips will be based on the SP5 socket and will be available in “B1” version.

From the parameters, it will use a similar core configuration as the existing Genoa chips, including 12 Zen 4 CCDs and an I / O chip, a total of 96 cores, with a TDP of 320W~400W.

Unlike regular Genoa chips, each Zen 4 CCD will have an additional 64MB 3D V-Cache stack (768MB total), including 1152MB L3 cache, 96MB L2 cache, in addition to 3MB of L1 cache (instruction/data), which is 2.6 times higher than the standard Genoa processor cache. It is even 56% larger than Milan-X (the first generation EPYC 3D V-Cache chip).

The AMD EPYC Genoa-X chip has a maximum frequency of 3.7 GHz, which is the same as the 96-core EPYC 9654 “Genoa” CPU, and the top model in the series should be the EPYC 9684X with 96 cores and 1152 MB of cache.

There is no more detailed information yet, AMD is expected to launch a new generation of Genoa-X chips in the middle of this year.

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First, the exposed AMD PPT introduces the naming rules for Skylar processors, taking the EPYC 9554X as an example.

9 for the product family, such as the 9004 series for the SP5 socket and the 8006 series for the SP6 socket.

Hundred digits 5 for the number of cores, e.g. 5 for 64 cores and 7 for 112-128 cores.

The tens digit 5 for relative performance.

4 for the number of generations.

X stands for characteristics, such as X for 3D cache, F for high frequency.

According to reports, AMD’s new generation of Skyline processors 9004 series will use the Zen4 architecture, available in 8 – 128 cores, including “Bergamo”, “Genoa” and “Genoa-X “Bergamo”, “Genoa” and “Genoa-X” types.

The EPYC 9754, codenamed “Bergamo”, will feature up to 128 Zen4C cores and up to 256 MB of L3 cache at up to 3.2 GHz with a 360W TDP. 40W.

The new Genoa-X series processors will feature 3D cache with up to 96 cores, with the flagship model being the 9684X, which has a large 1.1 GB of Level 3 cache and a TDP of 400W.

Sources say that the standard Genoa series should be launched in the next few months, and the Genoa-X series will not be launched until next year.

AMD has previously announced a new platform for Zen4 architecture data center CPUs with SP5 slots that support DDR5 memory as well as PCIe Gen5 and CXL interfaces. AMD’s 4th generation EPYC CPUs will be available in Genoa, Bergamo, Genoa-X and Siena, all based on the Zen4 architecture.

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