AMD will launch the EPYC Genoa-X series of server processors with 3D V-Cache this year, with a large 3D V-Cache cache and Zen 4 core, which will support DDR5 memory and PCIe Gen5 and CXL interfaces.

According to information released by Wccftech, the two AMD EPYC Genoa-X CPUs will have similar specifications and both chips will be based on the SP5 socket and will be available in “B1” version.

From the parameters, it will use a similar core configuration as the existing Genoa chips, including 12 Zen 4 CCDs and an I / O chip, a total of 96 cores, with a TDP of 320W~400W.

Unlike regular Genoa chips, each Zen 4 CCD will have an additional 64MB 3D V-Cache stack (768MB total), including 1152MB L3 cache, 96MB L2 cache, in addition to 3MB of L1 cache (instruction/data), which is 2.6 times higher than the standard Genoa processor cache. It is even 56% larger than Milan-X (the first generation EPYC 3D V-Cache chip).

The AMD EPYC Genoa-X chip has a maximum frequency of 3.7 GHz, which is the same as the 96-core EPYC 9654 “Genoa” CPU, and the top model in the series should be the EPYC 9684X with 96 cores and 1152 MB of cache.

There is no more detailed information yet, AMD is expected to launch a new generation of Genoa-X chips in the middle of this year.

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