The Hualien earthquake caused strong earthquakes to be felt throughout the island of Taiwan. The earthquakes were clearly felt in Fujian and Guangdong, and there were also earthquake feedback in Zhejiang, Jiangsu, Shanghai and other places. In addition, tsunamis have occurred in Japan’s Okinawa main island, Miyako Island and other places, and the wave height can reach about 3 meters.

Bloomberg reported that the Hualien earthquake caused the shutdown of some TSMC chip production lines, severely affecting the manufacturing of Apple’s 3nm chips.

Sources familiar with TSMC’s operations said that TSMC’s N3 wafer fab in Tainan suffered structural damage, with beams and columns broken, causing production to come to a complete halt. EUV lithography machines for processes below 7nm have also stopped operating, and the R&D laboratory There was also extensive damage, such as cracks in the walls. Another wafer fab in Hsinchu also suffered pipe ruptures and extensive damage, forcing it to suspend production.

Sources pointed out that some of TSMC’s high-end chips, such as Apple’s iPhone 15 Pro series equipped with A17 bionic chips, need to be produced in a stable vacuum environment for several weeks. Therefore, even if the earthquake does not cause direct damage, some chips that have already been put into production will be indirectly scrapped. .

Therefore, the direct impact of the Hualien earthquake on TSMC has triggered industry concerns about potential delays in the Apple product supply chain. Currently, TSMC has taken immediate action to assess the damage and initiate recovery procedures. Some production lines are expected to resume operations today, but the overall impact of the earthquake on Apple’s supply chain remains unclear.

It was previously reported that TSMC said that some factory areas have been evacuated and that all personnel are currently safe and have begun to return to work. Details are yet to be confirmed.

Bloomberg believes that Apple’s new generation 3nm chip is in the mass production stage before its release, so major disruptions in TSMC’s supply may delay the release of new products or limit supply.

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Samsung claims that wafer yields are between 60-70% during the development phase of the node. This number is critical to attracting customers whose wafer orders are based first on yield and second on cost per wafer.

Samsung is trying to rebuild confidence among chip designers after a controversy in 2022 about its engineering department “fabricating” yield figures to customers to win their business.

Samsung also said it will start introducing its 2nm node in 2025-2026 as 2023-2024 will be dominated by the 3nm node, known as SF3 (3GAP) and its improved version, SF3P (3GAP+).

Current customers for Samsung’s 3nm node include unnamed HPC processor designers and a mobile AP (application processor) designer.

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This is actually a report from Zyvex Labs in the United States.

On September 21, Zyvex Labs announced the launch of the world’s highest resolution lithography system – ZyvexLitho1. This tool uses quantum physics techniques to achieve atomic precision patterning and sub-nanometer (768 picometers – the width of a Si (100) 2 x 1 dimer row) resolution. width) resolution. This advancement allows quantum computers to provide unbreakable encryption for truly secure communications; such also faster drug discovery and more accurate weather forecasting.

The report further notes that ZyvexLitho1 is a scanning tunneling microscopy (STM: Scanning Tunneling Microscopy) based instrument that Zyvex Labs has been improving since 2007.

“There are many challenges in building scalable quantum computers. We strongly believe that high precision manufacturing is required to realize the full potential of quantum computing,” said Professor Michelle Simmons. “We are excited about ZyvexLitho1, the first commercial tool to provide atomic precision patterning.”

Professor Joe Lyding, the inventor of STM lithography, said, “To date, the Zyvex Labs technology is the most advanced and only commercial implementation of this atomically precise lithography.” Lyding is the 2014 Feynman Award winner and the Robert C. MacClinchie Distinguished Professor of Electrical and Computer Engineering at the University of Illinois.

Embedded in ZyvexLitho1 is our ZyVector, a 20-bit digital control system with low noise and low latency that enables our users to make atomically accurate patterns for solid-state quantum devices and other nanodevices and materials. The complete ZyvexLitho1 system also includes the ScientaOmicron ultra-high vacuum STM configured for fabricating quantum devices.

“I look forward to continuing our fruitful collaboration with Zyvex,” commented Dr. Andreas Bettac, SPM, ScientaOmicron Product Manager. “Here we are combining the latest UHV system designs and ScientaOmicron’s proven and mature SPM with Zyvex’s dedicated high-precision STM controller for STM-based lithography.”

As can be seen from the report, the product is also supported by DARPA (Defense Advanced Research Projects Agency), the Army Research Office, the Department of Energy’s Office of Advanced Manufacturing and Professor Reza Moheimani of the University of Texas at Dallas, who was recently awarded the Industrial Achievement Award by the International Federation of Automatic Control for “Support of Control Development for the Fabrication of Quantum Silicon Devices at the Single Atomic Scale”. The latter was recently awarded the International Federation of Automatic Control Award for “Control Development to Support the Fabrication of Quantum Silicon Devices at the Single Atomic Scale.

As you can see, this so-called 0.7nm chip may not be the same as the traditional chip manufacturing process.

Readers who understand the semiconductor industry should be clear that what we usually call how many nanometers, in fact, is a process node code. In the usual sense, this code is named with a number, followed by the abbreviation of a nanometer, such as 7nm, 5nm, 3nm, etc.

From about the 1960s to the late 1990s, nodes were named according to their gate length. This chart from the IEEE shows this relationship.

Semiconductor manufacturing involves huge capital expenditures and a lot of long-term research. The average length of time between the introduction of a new technical approach in paper and large-scale commercial manufacturing is about 10-15 years. Decades ago, the semiconductor industry recognized that it would be to everyone’s benefit if a common roadmap existed for node introduction and the size of the features that these nodes would target.

This would allow for extensive, simultaneous development of all the pieces of the puzzle needed to bring new nodes to market. For many years, the ITRS (International Technology Roadmap for Semiconductors) has published general roadmaps for the industry (which are no longer being updated). These roadmaps span 15 years and set overall goals for the semiconductor market.

For a long time, gate length (the length of a transistor gate) and half pitch (half the distance between two identical features on a chip) matched process node names, but the last time this happened was in 1997. the pitch continued to match node names for several generations but is no longer associated with it in any practical sense.

This shows that this is not quite the same as the process node we are familiar with in terms of process. This lithography is the so-called STM lithography.

Bypass EUV lithography?

From the relevant reports, it is pointed out that the lithography system to reach this 0.7 nm resolution is a technology called Hydrogen Depassivation Lithography, which is a kind of electron beam lithography (EBL), which can achieve atomic resolution.

According to Wikipedia, electron beam lithography (often abbreviated as EBL) is the practice of scanning a focused electron beam to draw custom shapes on a surface covered with an electron-sensitive film called a photoresist (exposure). The electron beam alters the solubility of the photoresist, allowing for the selective removal of exposed or unexposed areas by immersing the resist in a solvent (development). As with photolithography, the goal is to create very small structures in the resist, which are then typically transferred to the substrate material by etching.

The main advantage of electron beam lithography is that it can draw custom patterns with sub-10 nm resolution (direct write). This form of maskless lithography has high resolution and low throughput, limiting its use for photomask fabrication, low-volume production of semiconductor devices, and research and development.

The machine’s uses are described as making extremely precise structures for quantum dots-based quantum bits to achieve the highest quantum bit quality. The product can be used for other non-quantum-related applications, such as building nanopore membranes for biomedical and other chemical separation technologies.

As mentioned above, the drawback of the product is that the throughput is very low, in other words, it may be suitable for making small quantities of quantum processor chips, which is not a good solution for high-volume consumer electronics.

Zyvex Labs also says on its website that the system enables atomic precision lithography, among other things, UHV systems for STM lithography, precursor gas metrology and Si MBE, digital vector lithography and automation and scripting. They

This 7.7 nm (10 pixels) square exposure would not have been possible without sub-nanometer resolution and precision, they said.

Zyvex Labs notes that ZyvexLitho1 uses hydrogen depassivation lithography to remove H atoms from Si (100) 2×1 reconstructed surfaces. This self-developing exposure technique is inherently binary. the H-Si bond either breaks (sending the H atoms into a vacuum) or does not. There is no partial exposure or proximity effect.

Using this process and the global reference lattice as a silicon surface lattice allows digital lithography. A sub-nanometer pixel is 4 surface silicon atoms.

A computer-aided design (CAD) file with the same design lattice as our pixel lattice can be loaded into ZyvexLitho1 and the pattern can be automatically split into different geometries allowing tip vectors to be used with different lithography patterns. Exposure can then be performed automatically.

They also emphasize that the Si surface can be imaged before and after lithography because the lithography and imaging patterns are well separated in energy. This non-exposure imaging mode allows automatic identification of the Si lattice and therefore the position of the pixel on the surface. This Lattice Lock process automatically keeps tip positioning (and therefore lithography) accurate.

From the table they provide, the system has the following features.

So, the discussion on this comes back – can EBL replace traditional lithography?

Can EBL be a new choice?

The so-called photolithography is a patterning process in chip manufacturing. The process involves transferring the pattern from the photomask to the substrate. This is mainly done using steppers and scanners equipped with optical light sources, which is the mainstream chip manufacturing method we are now familiar with and is used in EUV and DUV.

Other forms of lithography include direct-write e-beam and nanoimprint. There are also several next-generation lithography (NGL) techniques in development – such as multi-beam e-beam and directional self-assembly (DSA).

According to NIST, electron beam lithography allows fine control of nanostructure features that form the basis for a variety of device technologies. Allowing 10 nm lateral resolution, 1 nm placement accuracy and 1 mm patterning area is possible.

However, achieving these performance metrics depends on many sample-specific interdependent factors – pattern definition and breakage, substrate and mask materials, pre- and post-exposure processes, alignment feature definition – as well as the operation of the critical detail lithography system.

As a core capability, NIST says it has developed processes at or near the limits of traditional electron-beam lithography to advance nanoscale devices and measurement science in a variety of fields.

Examples include chip-scale frequency combs for precision timing; nonlinear integrated optics for wavelength and quantum frequency conversion; on-chip cavity optomechanical and micro/nanoelectromechanical systems for sensing, conversion, and nonlinear dynamics studies; quantum photonic integrated circuits with nonlinear and quantum emitter light sources for quantum information; ultra-surfaces from the ultraviolet to the infrared for trapping and detecting atoms and ions, polarization measurements, imaging and Spatio-temporal ultrafast laser pulse shaping; and optical microscopy standards for aberration correction.

But its throughput and accuracy, as many reports suggest, limit the development of EBLs. According to a survey by the eBeam Initiative, the time to produce a mask writing using a direct writing device like EBL ranges from roughly 2.5 to 13 hours, with an average of 6.8 hours. According to the organization’s report, for complex masks, the maximum write time is 14 to 60 hours.

In general, manufacturers have headaches with mask designs that take longer than 24 hours to write. Because too long a write time means higher costs, longer processing time and yield problems.

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