In fact, in addition to increasing the number of layers, the means to increase storage density also include other solutions. At present, 4bit cell (QLC) type 3D NAND flash memory has been commercialized, and SSD has benefited from this and has become a “cabbage price”.

Although SSDs are showing signs of rising prices, several major manufacturers have begun to develop the next-generation 5-bit unit (PLC) solution, and I believe everyone will be able to use solid-state drives with larger capacity and faster speeds.

At the FMS 2023 Flash Memory Summit, SK Hynix demonstrated the results of its research on new PLC (5-Bit MLC) technology.

The principle of this technology is similar to the Twin BiCS FLASH technology developed by Kioxia in 2019. Simply put, it uses two 2.5 bit units, so that if two threads write at the same time, it will definitely be much faster than 5 bit storage.

In a 5 bit unit, a storage unit can contain 32 different threshold voltages (Note: 25), and the time required to write and verify 32 different threshold voltages with PLC in the conventional way is TLC. Nearly 20 times, which is obviously unacceptable to users.

Therefore, SK Hynix designed a new type of PLC that divides a 5bit unit into two 2.5 bit points, and each point also stores 2.5 bits. Then the data of each point is integrated to obtain 5 bit data, so that the writing time of PLC can be roughly the same as that of TLC (3bit unit).

In fact, Solidigm has demonstrated the first SSD using PLC-NAND a year ago, which uses the same 192-layer flash memory as the current QLC-NAND, but since each unit is composed of 5 bits (instead of 4 bits), its density increased to 23.3 Gbit/mm², setting a record high; and with the new 9th generation TLC-NAND with 321 layers, SK hynix is expected to reach a density of more than 20 Gbit/mm². Of course, more layers also mean more work steps and higher costs, and early products are expected to remain expensive.

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The new generation of memory chips can deliver transfer speeds of 2400MTps, and when used with high-end hosts, it can make consumer SSDs easily exceed 12GBps.

According to the report, the 8th generation V-NAND is available in a 1Tb (128GB) solution. Samsung Electronics has not disclosed the size and actual density of the IC, but they are calling it the highest bit density in the industry.

Samsung claims that its next-generation 3D NAND flash memory can increase single-crystal productivity by 20 percent compared to existing flash chips of the same capacity, which further reduces costs (at the same yield), which could mean that everyone can expect to buy a cheaper SSD of the same capacity.

The company did not reveal the architecture of the new product, but based on the images provided, we can assume it is a dual-plane 3D NAND chip.

As market demand for denser, higher-capacity storage drives higher V-NAND layer counts, Samsung employs advanced 3D compression technology to reduce surface area and height while avoiding the inter-cell interference that typically occurs during compression,” said SungHoi Hur, executive vice president of flash memory products and technologies at Samsung Electronics. ” “Our 8th generation V-NAND will help meet rapidly growing market demand and better position us to deliver more differentiated products and solutions that will be the foundation for future storage innovation.”

In the middle of this year, Samsung launched its eighth and ninth-generation V-NAND products, as well as its fifth-generation DRAM products. Prior to that, the company currently offered 512 Gb triple-level cell (TLC) products for V-NAND.

Other upcoming DRAM solutions from Samsung include 32 Gb DDR5 solutions, 8.5 Gbps LPDDR5X DRAM and 36 Gbps GDDR7 DRAM.

Samsung claims for its V-NAND that by 2030, it will have built 1,000 layers of V-NAND. To achieve this goal, Samsung is transitioning from its current TLC architecture to a quad-level cell (QLC) architecture to increase density and enable more layers.

Samsung will also invest more resources in DRAM R&D to investigate new architectures and materials, such as High-K, to help scale DRAM beyond 10nm. The company intends to further develop other DRAM solutions, such as processing in memory (PIM).

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