This alliance is TSMC’s sixth Open Innovation Platform (OIP) alliance. TSMC said that the 3D Fabric Alliance will help customers achieve rapid implementation of chip and system-level innovations, and use TSMC’s 3D Fabric technology consisting of a complete 3D silicon stack and advanced packaging technology series to achieve next-generation high-performance computing and mobile. application.

Most high-end processors are monolithic, but as the use of cutting-edge manufacturing technologies becomes more and more expensive, design methods are shifting to multi-chip modules. In the next few years, multi-chip system-in-packages (SiPs) are expected to become more widespread, and advanced 2.5D and 3D chip packaging technologies will become more important.

While multi-chip SiPs promise to simplify the development and verification of highly complex designs, they require entirely new development methods because 3D packaging presents many new challenges. This includes new design flows, new power delivery methods, new packaging techniques and new test techniques required for 3D integration. To take full advantage of TSMC’s 2.5D and 3D packaging technologies (InFO, CoWoS, and SoIC), the chip development industry needs the entire ecosystem to work together on chip packaging, and that’s what the 3DFabric Alliance is here for.

“Three-dimensional silicon stacking and advanced packaging technologies open the door to a new era of chip-level and system-level innovation, while also requiring broad ecosystem collaboration to help designers in There are countless options and ways to find the best path.”

TSMC’s 3DFabric Alliance brings together developers of electronic design automation (EDA) tools, intellectual property suppliers, contract chip designers, memory manufacturers, advanced substrate Equipment Manufacturing Group. The alliance currently has 19 members, but more new members are expected to join over time.

As the leader of the alliance, TSMC will set certain ground rules and standards. At the same time, members of the 3DFabric Alliance will jointly define and co-develop some specifications for TSMC’s 3D Fabric technology, and will be the first to receive TSMC’s 3D Fabric roadmap and specifications to align their plans with those of the fab and those of other members of the alliance. Consistent and able to design and optimize solutions compatible with new packaging methods.

Ultimately, TSMC wants to ensure that members of the 3D Fabric Alliance will provide its customers with compatible and interoperable solutions for rapid development and validation of multi-chip SiPs using 2.5D and 3D packaging.

For example, to unify the design ecosystem with qualified EDA tools and processes, TSMC developed its 3Dblox standard. 3Dblox covers all aspects of building multi-chip devices using 2.5D and 3D packaging methods, such as chip and interface definition, including physical implementation, power consumption, thermal dissipation, electromigration IR drop (EMIR), and timing/physical verification.

Ultimately, TSMC envisions that the alliance will greatly simplify and streamline the process of developing more advanced chips, especially for small and medium-sized companies that rely more on external IP/design. E.g,

While big companies like AMD and Nvidia tend to develop their own IP, interconnect and packaging technologies, multi-chip SiP promises to enable smaller companies to develop complex chip-based processors as well. For them, standard third-party IP, fast time-to-market and proper integration are the keys to success, so the 3D Fabric Alliance is critical to them.

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