According to foreign technology media SamMobile report, Samsung plans to use fan-out wafer-level packaging (FoWLP) technology for the Exynos 2400 processor.
FoWLP means smaller package size, higher integration, and can provide I/O performance. Theoretically, the Exynos 2400 processor is smaller, more powerful, and more energy efficient.
Mini-lesson (the following is from Wikipedia):
Fan-out wafer-level packaging is an integrated circuit packaging technology that is an enhancement to the standard wafer-level packaging solution. In traditional technology, the wafer is first cut and then the individual cores are packaged; then, the individual cores are packaged on the wafer. The package size is typically much larger than the chip size.
In contrast, in a standard WLP process, the IC remains part of the wafer when it is packaged, and then the wafer is cut into smaller pieces. The final package is effectively the same size as the die itself.
According to previously available information, the Exynos 2400 processor features a 1+2+3+4 design:
- 1 Cortex-X4 core, clocked at 3.1GHz
- 2 Cortex-A720 cores clocked at 2.9GHz
- 3 Cortex-A720 cores clocked at 2.6GHz
- 4 Cortex-A520 cores clocked at 1.8GHz
The Exynos 2400 will use an RDNA2 GPU called Xclipse X940 (tentative) with 6 WGP (12 CU), 8 MB L3 cache, and hardware-level ray tracing support.
