Qualcomm today issued a press release, claiming that it is working with Google to develop a Snapdragon Wear chip based on RISC-V architecture, this new chip will be used in the next generation of Wear OS watches.
▲ Source Qualcomm official website
RISC-V is the third largest CPU architecture besides x86 and Arm, and previously Calista Redmond, CEO of RISC-V International, claimed that “as a global standard, RISC-V is not subject to the control of any single company or country”.
Qualcomm plans to commercialize RISC-V-based wearable solutions globally, and the RISC-V Snapdragon Wear chip is said to deliver “custom cores, low power consumption, and high performance” that are essential for smartwatches.
Qualcomm has been a pillar of the Wear OS ecosystem, delivering high-performance, low-power systems to many of our OEM partners, and we’re excited to expand our collaboration with Qualcomm and introduce RISC-V-based wearable solutions,” said Bjorn Kilburn, general manager, Wear OS by Google. “
Qualcomm and Google recently launched the RISC-V Software Ecosystem (RISE), which is reportedly driving a range of RISC-V hardware development.
As an open-source instruction set architecture (ISA), RISC-V encourages innovation by allowing any company to develop a fully customized core.
This enables more companies to enter the market, leading to more innovation and competition in the industry.
The openness, flexibility and scalability of RISC-V benefits the entire value chain, from silicon suppliers to OEMs, end devices and consumers.The latest RISC-V chips on the market still fall short of flagship Arm architecture processors in terms of performance and features, but Qualcomm and Google’s smartwatch announcements show that both companies believe RISC-V chips are ready for wearables and that the openness of the RISC-V architecture is relatively more cost-effective for devices.
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