Synopsys announced today that the digital and custom design process has been certified by TSMC’s upgraded 3-nanometer (N3E) process. This process and its underlying and interface IP portfolio have been successfully taped out many times in TSMC’s N3E process, which can help customers accelerate R&D.
Dan Kochpatcharin, head of TSMC’s design infrastructure management department, said that Synopsys’ latest achievements in electronic design automation (EDA) and IP on TSMC’s N3E process technology bring powerful solutions to mutual customers to help them meet innovative designs. stringent power, performance, and area targets.
TSMC’s 3-nanometer process will be mass-produced this quarter (Q4). TSMC President Wei Zhejia previously stated that the N3E technology development progress is ahead of schedule and is expected to be mass-produced in the second half of 2023.
Synopsys is an American electronic design automation company and IC interface IP supplier, focusing on chip design and verification, chip intellectual property and computer security, and has nothing to do with Cisco.
Sanjay Bali, vice president of marketing strategy for Synopsys’ Silicon Realization Group, said the recent results represent another important milestone in the continued successful collaboration between Synopsys and TSMC, bringing designers a way to meet their key design requirements.
Synopsys said TSMC’s N3E process expands its 3nm process family with better power consumption, performance and yield for workload-intensive applications such as high-performance computing, AI artificial intelligence and mobility.
