Marvell last week launched a programmable switch chip called “the industry’s lowest latency” Teralynx 10. This is a 51.2T switch chip designed for the 800GbE era.
It’s a 51.2 Tbps programmable 5nm chip designed to address operators’ bandwidth explosion while meeting stringent power and cost requirements. It is suitable for leaf and spine applications in next-generation data center networks, as well as AI/ML and high-performance computing (HPC) fabrics.
According to reports, a Teralynx 10 is equivalent to 12 12.8 Tbps generation chips, which can reduce power consumption by 80% under the same capacity.
Teralynx 10 features 512 long reach (LR) 112G SerDes with the industry’s lowest bit error rate (BER). With it, Switch Systems can develop more comprehensive switch configurations such as 32 x 1.6T, 64 x 800G and 128 x 400G links, giving suppliers the flexibility to meet each operator’s unique needs.
It features an ultra-low-latency fabric, is compatible with Teralynx software, and also supports Teralynx Flashlight advanced telemetry, including P4 in-band network telemetry (INT).
According to reports, Teralynx 7th generation switches have shipped about 5 million 400GbE ports, and Teralynx 10 will provide samples in the second quarter.
The existing PCIe Gen5 speed only supports 400GbE links. It is expected to see 800GbE or even higher-level mainstream servers and storage devices when PCIe Gen6 comes out in 2-3 years.