AMD recently participated in the International Solid-State Circuits Conference (ISSCC) conference and shared a die shot photo of the cIOD (I/O interface die) on the Zen 4 processor in the presentation.
die shot A photograph or record of the layout of an integrated circuit showing its internal design after all packaging has been removed. A die shot diagram to compare a die to a cross-section of a two-dimensional computer chip where the design and construction of the various tracks and components can be clearly seen.
Foreign professional netizen Locuza also provided detailed annotations on this photo. However, the pictures released this time are not too surprising. Zen 4 cIOD includes an RDNA 2 WGP, which contains four 40-bits DDR5 memory channels.
The HotHardWare reports that Zen 4 cIOD shows that the chip has 2 GMI3 ports. GMI3 is the interface used to connect the CCD (Core Complex Dice hosting the Zen 4 core) to the cIOD. This means you can’t use an existing cIOD to handle more than two CCDs, contrary to past rumors that AMD was considering such a processor.
The Zen 4 cIOD actually only has 28 lanes of PCIe 5, compared to 32 lanes on previous generations of chips, but only 28 are active. This may indicate that AMD is very confident in the maturity of the 6nm process for manufacturing cIODs.
