The AMD Ryzen 7000 series not only brought a 5nm process, Zen4 architecture, RDNA2 GPU core, DDR5 memory, PCIe 5.0 bus, and AM5 interface but also added the AVX-512 instruction set for the first time, which was Intel’s unique skill before. Recently, AMD updated the basic code of the Linux GCC compiler, which is equivalent to a small patch for the new Zenver4, adding support for the AVX-512 instruction set.
Specific supported instructions include AVX512F, AVX512DQ, AVX512IFMA, AVX512CD, AVX512BW, AVX512VL, AVX512BF16, AVX512VBMI, AVX512VBMI2, GFNI, AVX512VNNI, AVX512BITALG, AVX512VPOPCNTDQ.
The next-generation Snapdragon 9004 series with the same Zen4 architecture to be released at the end of the year will also bring the AVX-512 instruction set to AMD’s server and data center solutions.
It is worth mentioning that it is also the AVX-512 instruction set. Intel is a complete 512-bit channel, and AMD has cut it to 256-bit. Therefore, when executing 512-bit instructions, it needs to be split into two 256-bit instructions. , The official said that this can save chip area, avoid excessive heat and reduce performance.
Among the many new instructions, VNNI and BF16 are for AI acceleration. The official claim is that the multi-thread performance of FP32 floating-point inference can be improved by 1.31 times, and the multi-threaded performance of VNNI INT8 integer inference can be improved by 2.47 times!
