AMD’s fifth-generation EPYC processor “Turin” will continue to use the existing SP5 platform, which is in line with AMD’s strategy of using the same socket for two generations of server CPUs, and its successor product “Venice” is expected to use the new SP7 platform.
@元城安素-YuuKi_AnS has obtained AMD’s latest data center roadmap. AMD’s sixth-generation EPYC processor is code-named “Venice”. This series of processors is based on the next-generation Zen 6 core and will use the new SP7 socket.
He asserted that the new platform will support up to 16 memory channels, support DDR5 and new types of memory (Note: such as MR-DIMM and MCR-DIMM), and even if the new processor has hundreds of cores, it can still ensure sufficient memory. bandwidth.
Taking into account the increase in the number of cores, we expect that the new SP7 platform will bring significant power supply enhancements to the Venice processor. Given that SP5 has a maximum power supply capability of up to 700W, it is expected that AMD’s sixth-generation EPYC processors may have a significant improvement.
However, we still know very little about the SP7 processor. Considering that SP5 has 6096 pins, it can be assumed that the new platform will use a larger number of pins, and may also use a larger CPU package, thereby increasing the number of cores and functions.
Zen3 Zen4 Zen5 Zen6
Codename 7003 “Milan(-X)” 9004 “Genoa(-X)”
8004 “Bergamo”
8004 “Siena” 9005 “Turin(-X)”
8005 “Turin-Dense” 9006 “Venice”
Date 2021 2023 2024+ 2025+
Platform SP3 (LGA4094) SP5 (LGA-6096)
SP6 (LGA 4094) SP5 (LGA-6096)
SP6 (LGA 4094) SP7
Core 64C 96C/128C 128C/192C TBC
Memory 8C DDR4 12C DDR5 12C DDR5 16C DDR5
